Publications Academic Year 2005 (Sakai & Goshima Lab.)

JournalsInternationalDomestic

Journals

  1. Shuichi Sakai:
    “Evolution of New Generation Processor Architecture”
    IPSJ Magazine [Joho Shori], Vol.46, No.10, pp.1100-1103, Oct, 2005.
  2. Masahiro Goshima:
    “Superscalar / VLIW and Troughput-Oriented Multithreaded Processors”
    IPSJ Magazine [Joho Shori], Vol.46, No.10, pp.1104-1110, Oct, 2005.
  3. Hidetsugu Irie:
    “Clustered Microarchitecture”
    IPSJ Magazine [Joho Shori], Vol.46, No.10, pp.1111-1117, Oct, 2005.
  4. Poonacha Kongetira, Kathigamar Aingaran, Kunle Olukotum, Shuichi Sakai (translation) and Masahiro Goshima (translation):
    “NIAGARA: A 32-Way Multithreaded SPARC Processor”
    IPSJ Magazine [Joho Shori], Vol.46, No.11, pp.1236-1243, Nov, 2005.
  5. Yi Ge, Takao Sakurai, Luong Dinh Hung, Koki Abe and Shuichi Sakai:
    “Evaluation of Hardware Implementations for Interleaved Modular Multiplication”
    IEICE Transactions, Vol.J88-A, No.12, pp.1497-1505, Dec, 2005.
    [ pdf ]
  6. Naoya Hatta, Niko Demus Barli, Chitaka Iwama, Luong Dinh Hung, Daisuke Tashiro, Shuichi Sakai and Hidehiko Tanaka:
    “Bus Serialization for Reducing Power Consumption”
    IPSJ Transactions on Advanced Computing Systems(ACS 13), Vol.47, No.SIG3, Mar, 2006.
    [ pdf ]

International Conferences, Workshops

  1. Hidetsugu Irie, Naoya Hattori, Masanori Takada, Naoya Hatta, Takeshi Toyoshima, Shuichi Sakai:
    “Distributed Speculative Memory Forwarding”
    IEEE Symp. on Low-Power and High-Speed Chips(COOL Chips VIII), at Yokohama Joho Bunka Center, pp.473-482, Apr, 2005.
    [ pdf ]
  2. Luong Dinh Hung, Masahiro Goshima and Shuichi Sakai:
    “Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag”
    IEEE International Conference on Computer Design (ICCD 2005), at San Jose, California, USA, Vol.2005, pp.342-347, Oct, 2005.
    [ pdf ]
  3. Luong Dinh Hung and Shuichi Sakai:
    “Dynamic Estimation of Task Level Parallelism with Operating System Support”
    International Symposium on Parallel Architectures, Algorithms, and Networks (ISPAN 2005), at Las Vegas, Nevada, USA, Vol.2005, pp.358-363, Dec, 2005.
    [ pdf ]

Domestic Conferences, Workshops

  1. Yuya Ueno, Luong D. Hung, Masanori Takada, Daisuke Tashiro and Shuichi Sakai:
    “Improvement of Signature-based Phase Detection and its Application to Power Reduction in Caches” IEICE Technical Report RECONF2005-1～14, at Kyoto University, Vol.105, No.42, pp.25-30, May, 2005.
    [ pdf ]
  2. Kazuto Shimizu, Masanori Takada, Hidetsugu Irie and Shuichi Sakai:
    “Dynamic Address Translation for Hiding Behavior of Programs” IPSJ SIG Technical Reports 2005-ARC-164, at Takeo City Bunka Kaikan, Vol.2005, No.80, pp.19-24, Aug, 2005.
    [ pdf ]
  3. Taihei Momma, Luong Dinh Hung, Daisuke Tashiro and Shuichi Sakai:
    “Verification of Cache Coherency Protocol for Speculative Multithreading” IPSJ SIG Technical Reports 2005-ARC-164, at Takeo City Bunka Kaikan, Vol.2005, No.80, pp.103-108, Aug, 2005.
    [ pdf ]
  4. Luong D. Hung, Masahiro Goshima and Shuichi Sakai:
    “Technique to Mitigate Soft Errors in Caches with CAM-based Tags” IEICE Technical Report DC2005-18, at Takeo City Bunka Kaikan, Vol.105, No.227, pp.31-36, Aug, 2005.
    [ pdf ]