src/Emu/PPC64Linux/PPC64Converter.cpp

説明を見る。
00001 // 
00002 // Copyright (c) 2005-2008 Kenichi Watanabe.
00003 // Copyright (c) 2005-2008 Yasuhiro Watari.
00004 // Copyright (c) 2005-2008 Hironori Ichibayashi.
00005 // Copyright (c) 2008-2009 Kazuo Horio.
00006 // Copyright (c) 2009-2013 Naruki Kurata.
00007 // Copyright (c) 2005-2013 Ryota Shioya.
00008 // Copyright (c) 2005-2013 Masahiro Goshima.
00009 // 
00010 // This software is provided 'as-is', without any express or implied
00011 // warranty. In no event will the authors be held liable for any damages
00012 // arising from the use of this software.
00013 // 
00014 // Permission is granted to anyone to use this software for any purpose,
00015 // including commercial applications, and to alter it and redistribute it
00016 // freely, subject to the following restrictions:
00017 // 
00018 // 1. The origin of this software must not be misrepresented; you must not
00019 // claim that you wrote the original software. If you use this software
00020 // in a product, an acknowledgment in the product documentation would be
00021 // appreciated but is not required.
00022 // 
00023 // 2. Altered source versions must be plainly marked as such, and must not be
00024 // misrepresented as being the original software.
00025 // 
00026 // 3. This notice may not be removed or altered from any source
00027 // distribution.
00028 // 
00029 // 
00030 
00031 
00032 #include <pch.h>
00033 
00034 #include "Emu/PPC64Linux/PPC64Converter.h"
00035 
00036 #include "Emu/Utility/GenericOperation.h"
00037 #include "Emu/Utility/OpEmulationState.h"
00038 
00039 #include "Emu/PPC64Linux/PPC64Info.h"
00040 #include "Emu/PPC64Linux/PPC64OpInfo.h"
00041 #include "Emu/PPC64Linux/PPC64Decoder.h"
00042 #include "Emu/PPC64Linux/PPC64Operation.h"
00043 
00044 using namespace std;
00045 using namespace boost;
00046 using namespace Onikiri;
00047 using namespace Onikiri::EmulatorUtility;
00048 using namespace Onikiri::PPC64Linux;
00049 using namespace Onikiri::EmulatorUtility::Operation;
00050 using namespace Onikiri::PPC64Linux::Operation;
00051 
00052 //
00053 // `
00054 //
00055 //
00056 namespace {
00057     // XO = extra opcode
00058 
00059     // e`ョIyR[h}XN (0rbg)
00060     const u32 MASK_EXACT  = 0xffffffff; // Sbitv
00061     const u32 MASK_OP     = 0xfc000000; // opcode 
00062     const u32 MASK_OPF    = 0xfc000001; // opcode  Rc
00063     const u32 MASK_B      = 0xfc000003; // I-Form unconditional branch
00064     const u32 MASK_MD     = 0xfc00001d; // MD-Form (opcode, 3-bit XO, Rc)
00065     const u32 MASK_MDS    = 0xfc00001f; // MDS-Form (opcode, 4-bit XO, Rc)
00066     const u32 MASK_X2     = 0xfc000003; // 2rbgXO (DS-Form)
00067     const u32 MASK_XS9    = 0xfc0007fc; // XS-Form (9-bit XO)
00068 //  const u32 MASK_X10SH  = 0xfc0007fc; // XO10 - sh (XO 1rbg sh gp)
00069     const u32 MASK_X10    = 0xfc0007fe; // 10rbgXO
00070 
00071 //  const u32 MASK_X10LK  = 0xfc0007ff; // XO10 + LK (Link Register write)
00072 
00073     const u32 MASK_X10OE  = 0xfc0003fe; // XO10 - OE (XO 1rbg OE gp)
00074     const u32 MASK_X10MB  = 0xfc00001e; // XO10 - MB (XO 6rbg MB/ME gp)
00075     const u32 MASK_X10MBSH = 0xfc00001c;    // XO10 - MB - SH
00076 
00077     const u32 MASK_X5F    = 0xfc00003f; // XO5 + Rc (FP A-Form instructions)
00078     const u32 MASK_X10F   = 0xfc0007ff; // XO10 + Rc (flag write)
00079     const u32 MASK_X10FOE = 0xfc0003ff; // XO10 - OE + Rc
00080     const u32 MASK_X10FSH = 0xfc0007fd; // XO10 - sh + Rc
00081     const u32 MASK_X10FMB = 0xfc00001f; // XO10 - MB (XO 6rbg MB/ME gp)
00082     const u32 MASK_X10FMBSH = 0xfc00001d;   // XO10 - MB - SH + Rc
00083 
00084     const u32 MASK_MTFSPR = 0xfc1ffffe; // mtspr/mfspr
00085     const u32 MASK_MTCRF  = 0xfc1ff7fe; // mtcrf
00086     const u32 MASK_DCMP   = 0xfc200000; // D-Form compare (opcode, 32/64-bit flag)
00087     const u32 MASK_X10CMP = 0xfc2007fe; // X-Form compare (opcode, 32/64-bit flag, 10-bit XO)
00088 
00089     const u32 MASK_RA     = 0x001f0000; // RAu (RA=0 gp)
00090 }
00091 #define MASK_BC(mask_bo) (MASK_B | (mask_bo) << 21)
00092 #define MASK_BCLR(mask_bo) (MASK_X10 | (mask_bo) << 21 | 0x3 << 11 | 0x1)
00093 
00094 // B-Form conditional branch
00095 #define OPCODE_OP(c) (u32)((c) << 26)
00096 #define OPCODE_OPF(c, f) (u32)(OPCODE_OP(c) | (f))
00097 #define OPCODE_B(c, aa, lk) (u32)(OPCODE_OP(c) | (aa) << 1 | (lk))
00098 #define OPCODE_BC(c, aa, lk, bo) (u32)(OPCODE_B(c, aa, lk) | (bo) << 21)
00099 
00100 #define OPCODE_MD(c, x, f) (u32)(OPCODE_OP(c) | (x) << 2 | (f))
00101 #define OPCODE_MDS(c, x, f) (u32)(OPCODE_OP(c) | (x) << 1 | (f))
00102 #define OPCODE_X2(c, x) (u32)(OPCODE_OP(c) | (x))
00103 #define OPCODE_X5(c, x) (u32)(OPCODE_OP(c) | (x) << 1)
00104 #define OPCODE_XS9(c, x) (u32)(OPCODE_OP(c) | (x) << 2)
00105 #define OPCODE_X10(c, x) (u32)(OPCODE_OP(c) | (x) << 1)
00106 #define OPCODE_X10OE(c, x, oe) (u32)(OPCODE_X10(c,x) | (oe) << 10)
00107 #define OPCODE_X10FOE(c, x, oe, f) (u32)(OPCODE_X10OE(c,x,oe) | (f))
00108 #define OPCODE_X5F(c, x, f) (u32)(OPCODE_X5(c, x) | (f))
00109 #define OPCODE_XS9F(c, x, f) (u32)(OPCODE_XS9(c, x) | (f))
00110 #define OPCODE_X10F(c, x, f) (u32)(OPCODE_X10(c, x) | (f))
00111 
00112 #define OPCODE_BCLR(c, xo, lk, bo, bh) (u32)(OPCODE_X10(c, xo) | (bo) << 21 | (bh) << 11 | (lk))
00113 
00114 #define OPCODE_MTFSPR(c, xo, spr) (u32)(OPCODE_X10(c, xo) | ((spr) & 0x01f) << 16 | ((spr) & 0x3e0) >> 5 << 11)
00115 #define OPCODE_DCMP(c, L) (u32)(OPCODE_OP(c) | (L) << 21)
00116 #define OPCODE_X10CMP(c, x, L) (u32)(OPCODE_X10(c, x) | (L) << 21)
00117 #define OPCODE_MTCRF(c, xo, crf) (u32)(OPCODE_X10(c, xo) | (crf) << 12)
00118 
00119 namespace {
00120     // Iyhev[g
00121     // [RegTemplateBegin, RegTemplateEnd] CIyhWX^u
00122     // [ImmTemplateBegin, RegTemplateEnd] Clu
00123 
00124     // WX^Eev[ggp
00125     // {WX^g
00126     static const int RegTemplateBegin = -20;    // WX^ (lD{WX^d)
00127     static const int RegTemplateEnd = RegTemplateBegin+4-1;
00128     static const int ImmTemplateBegin = -30;    // l
00129     static const int ImmTemplateEnd = ImmTemplateBegin+4-1;
00130 
00131     const int R0 = RegTemplateBegin+0;
00132     const int R1 = RegTemplateBegin+1;
00133     const int R2 = RegTemplateBegin+2;
00134     const int R3 = RegTemplateBegin+3;
00135 
00136     const int I0 = ImmTemplateBegin+0;
00137     const int I1 = ImmTemplateBegin+1;
00138     const int I2 = ImmTemplateBegin+2;
00139     const int I3 = ImmTemplateBegin+3;
00140 
00141     const int CR0 = PPC64Info::REG_CR0;
00142     const int CR1 = CR0 + 1;
00143     const int CR2 = CR0 + 2;
00144     const int CR3 = CR0 + 3;
00145     const int CR4 = CR0 + 4;
00146     const int CR5 = CR0 + 5;
00147     const int CR6 = CR0 + 6;
00148     const int CR7 = CR0 + 7;
00149 
00150     const int LR = PPC64Info::REG_LINK;
00151     const int CTR = PPC64Info::REG_COUNT;
00152     //const int XER = PPC64Info::REG_XER;
00153     const int FPC = PPC64Info::REG_FPSCR;
00154     const int CA = PPC64Info::REG_CA;
00155     const int AR = PPC64Info::REG_ADDRESS;
00156 }
00157 
00158 #define PPC64DSTOP(n) DstOperand<n> 
00159 #define PPC64SRCOP(n) SrcOperand<n> 
00160 #define PPC64SRCOPFLOAT(n) Cast< float, AsFP< double, SrcOperand<n> > >
00161 #define PPC64SRCOPDOUBLE(n) AsFP< double, SrcOperand<n> >
00162 
00163 #define D0 PPC64DSTOP(0)
00164 #define D1 PPC64DSTOP(1)
00165 #define D2 PPC64DSTOP(2)
00166 #define S0 PPC64SRCOP(0)
00167 #define S1 PPC64SRCOP(1)
00168 #define S2 PPC64SRCOP(2)
00169 #define S3 PPC64SRCOP(3)
00170 #define S4 PPC64SRCOP(4)
00171 #define S5 PPC64SRCOP(5)
00172 #define SF0 PPC64SRCOPFLOAT(0)
00173 #define SF1 PPC64SRCOPFLOAT(1)
00174 #define SF2 PPC64SRCOPFLOAT(2)
00175 #define SF3 PPC64SRCOPFLOAT(3)
00176 #define SF4 PPC64SRCOPFLOAT(4)
00177 #define SF5 PPC64SRCOPFLOAT(5)
00178 #define SD0 PPC64SRCOPDOUBLE(0)
00179 #define SD1 PPC64SRCOPDOUBLE(1)
00180 #define SD2 PPC64SRCOPDOUBLE(2)
00181 #define SD3 PPC64SRCOPDOUBLE(3)
00182 #define SD4 PPC64SRCOPDOUBLE(4)
00183 #define SD5 PPC64SRCOPDOUBLE(5)
00184 
00185 // 60000000 ori r0, r0, 0 = nop
00186 
00187 // no trap implemented
00188 
00189 // @ItFb`G[CタsG[
00190 // syscallCOタs (タs@I)
00191 PPC64Converter::OpDef PPC64Converter::m_OpDefUnknown = 
00192     {"unknown", MASK_EXACT, 0,  1, {{OpClassCode::UNDEF,    { -1, -1, -1}, {I0, -1, -1, -1, -1, -1},    PPC64Converter::PPC64UnknownOperation}}};
00193 
00194 
00195 // branchCOpInfo 
00196 PPC64Converter::OpDef PPC64Converter::m_OpDefsBase[] = 
00197 {
00198     // system call
00199     // r0 = id
00200     // r3-r8 = args
00201     // r3 = ret value
00202     // CR0:so = error
00203     {"sc",  MASK_OP, OPCODE_OP(17), 2, {
00204         {OpClassCode::syscall,  {-1, -1}, { 0,  3,  4, -1, -1, -1}, PPC64SyscallSetArg},
00205         {OpClassCode::syscall_branch,   { 3,CR0}, { 5,  6,  7,  8, -1, -1}, PPC64SyscallCore},
00206     }},
00207 
00208     //
00209     // special instructions
00210     //
00211     {"nop",     MASK_EXACT, 0x60000000, 1, {{OpClassCode::iNOP, { -1, -1, -1}, { -1, -1, -1, -1, -1, -1},   NoOperation}}},
00212     //{"fnop",  MASK_EXACT, 0xxxxxxxxx, 1, {{OpClassCode::fNOP, { -1, -1, -1}, { -1, -1, -1, -1, -1, -1},   NoOperation}}},
00213     //{"unop",  MASK_EXACT, 0xxxxxxxxx, 1, {{OpClassCode::iNOP, { -1, -1, -1}, { -1, -1, -1, -1, -1, -1},   NoOperation}}},
00214 
00215 
00216     //
00217     // integer
00218     //
00219 
00220     // - gpH : td, tdi, tw, twi, isel, div, lmw, smw, string load/store, byte-reversal load/store
00221     //                              OE=1 
00222 
00223     // arithmetic
00224 
00225     // addi, adds  RA=0 
00226     {"li",      MASK_OP | MASK_RA, OPCODE_OP(14), 1, {{OpClassCode::iIMM,  { R0, -1, -1}, { I0, -1, -1, -1, -1, -1}, Set< D0, S0 >}}},
00227     {"lis",     MASK_OP | MASK_RA, OPCODE_OP(15), 1, {{OpClassCode::iIMM,  { R0, -1, -1}, { I0, -1, -1, -1, -1, -1}, Set< D0, LShiftL< u64, S0, IntConst<unsigned int,16>, 63> >}}},
00228 
00229     {"addi",    MASK_OP, OPCODE_OP(14), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0, IntAdd< u64, S0, S1 > >}}},
00230     {"adds",    MASK_OP, OPCODE_OP(15), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0, IntAdd< u64, S0, LShiftL< u64, S1, IntConst<unsigned int,16>, 63> > >}}},
00231 
00232     {"add",     MASK_X10FOE, OPCODE_X10FOE(31, 266, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1},       Set< D0,     IntAdd< u64, S0, S1 > >}}},
00233     {"add.",    MASK_X10FOE, OPCODE_X10FOE(31, 266, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, IntAdd< u64, S0, S1 > >}}},
00234     
00235     {"subf",    MASK_X10FOE, OPCODE_X10FOE(31,  40, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1},       Set< D0,     IntSub< u64, S1, S0 > >}}},
00236     {"subf.",   MASK_X10FOE, OPCODE_X10FOE(31,  40, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, IntSub< u64, S1, S0 > >}}},
00237 
00238     {"addic",   MASK_OP, OPCODE_OP(12), 1, {{OpClassCode::iALU,  { R0, CA, -1}, { R1, I0, -1, -1, -1, -1}, 
00239         Sequence2<
00240                   Set< D1,     CarryOfAdd< u64, S0, S1 > >,
00241                   Set< D0,     IntAdd< u64, S0, S1 > >
00242         >
00243     }}},
00244     {"addic.",  MASK_OP, OPCODE_OP(13), 1, {{OpClassCode::iALU,  { R0, CA,CR0}, { R1, I0, -1, -1, -1, -1}, 
00245         Sequence2<
00246                   Set< D1,     CarryOfAdd< u64, S0, S1 > >,
00247             PPC64SetF< D0, D2, IntAdd< u64, S0, S1 > >
00248         >
00249     }}},
00250 
00251     // Carry Flag  Borrow Flag gp
00252     {"subfic",  MASK_OP, OPCODE_OP(8), 1, {{OpClassCode::iALU,  { R0, CA, -1}, { R1, I0, -1, -1, -1, -1}, 
00253         Sequence2<
00254                   Set< D1,     BitXor< u64, BorrowOfSub< u64, S1, S0>, IntConst<u64, (u64)1> > >,
00255                   Set< D0,     IntSub< u64, S1, S0 > >
00256         >
00257     }}},
00258 
00259     {"addc",    MASK_X10FOE, OPCODE_X10FOE(31,  10, 0, 0), 1, {{OpClassCode::iALU,  { R0, CA, -1}, { R1, R2, -1, -1, -1, -1}, 
00260         Sequence2<
00261                   Set< D1,     CarryOfAdd< u64, S0, S1 > >,
00262                   Set< D0,     IntAdd< u64, S0, S1 > >
00263         >
00264     }}},
00265     {"addc.",   MASK_X10FOE, OPCODE_X10FOE(31,  10, 0, 1), 1, {{OpClassCode::iALU,  { R0, CA,CR0}, { R1, R2, -1, -1, -1, -1}, 
00266         Sequence2<
00267                   Set< D1,     CarryOfAdd< u64, S0, S1 > >,
00268             PPC64SetF< D0, D2, IntAdd< u64, S0, S1 > >
00269         >
00270     }}},
00271     {"subfc",   MASK_X10FOE, OPCODE_X10FOE(31,   8, 0, 0), 1, {{OpClassCode::iALU,  { R0, CA, -1}, { R1, R2, -1, -1, -1, -1}, 
00272         Sequence2<
00273                   Set< D1,     BitXor< u64, BorrowOfSub< u64, S1, S0>, IntConst<u64, (u64)1> > >,
00274                   Set< D0,     IntSub< u64, S1, S0 > >
00275         >
00276     }}},
00277     {"subfc.",  MASK_X10FOE, OPCODE_X10FOE(31,   8, 0, 1), 1, {{OpClassCode::iALU,  { R0, CA,CR0}, { R1, R2, -1, -1, -1, -1}, 
00278         Sequence2<
00279                   Set< D1,     BitXor< u64, BorrowOfSub< u64, S1, S0>, IntConst<u64, (u64)1> > >,
00280             PPC64SetF< D0, D2, IntSub< u64, S1, S0 > >
00281         >
00282     }}},
00283 
00284     {"adde",    MASK_X10FOE, OPCODE_X10FOE(31, 138, 0, 0), 1, {{OpClassCode::iALU,  { R0, CA, -1}, { R1, R2, CA, -1, -1, -1}, 
00285         Sequence2<
00286                   Set< D1,     CarryOfAddWithCarry< u64, S0, S1, S2 > >,
00287                   Set< D0,     IntAdd< u64, IntAdd< u64, S0, S1 >, S2> >
00288         >
00289     }}},
00290     {"adde.",   MASK_X10FOE, OPCODE_X10FOE(31, 138, 0, 1), 1, {{OpClassCode::iALU,  { R0, CA,CR0}, { R1, R2, CA, -1, -1, -1}, 
00291         Sequence2<
00292                   Set< D1,     CarryOfAddWithCarry< u64, S0, S1, S2 > >,
00293             PPC64SetF< D0, D2, IntAdd< u64, IntAdd< u64, S0, S1 >, S2> >
00294         >
00295     }}},
00296     // BitXor< u64, S2, IntConst<u64, (u64)1> > = BO = !CA
00297     {"subfe",   MASK_X10FOE, OPCODE_X10FOE(31, 136, 0, 0), 1, {{OpClassCode::iALU,  { R0, CA, -1}, { R1, R2, CA, -1, -1, -1}, 
00298         Sequence2<
00299                   Set< D1,     BitXor< u64, BorrowOfSubWithBorrow< u64, S1, S0, BitXor< u64, S2, IntConst<u64, (u64)1> > >, IntConst<u64, (u64)1> > >,
00300                   Set< D0,     IntSub< u64, S1, IntAdd< u64, S0, BitXor< u64, S2, IntConst<u64, (u64)1> > > > >     // lhs - (rhs+BO)
00301         >
00302     }}},
00303     {"subfe.",  MASK_X10FOE, OPCODE_X10FOE(31, 136, 0, 1), 1, {{OpClassCode::iALU,  { R0, CA,CR0}, { R1, R2, CA, -1, -1, -1}, 
00304         Sequence2<
00305                   Set< D1,     BitXor< u64, BorrowOfSubWithBorrow< u64, S1, S0, BitXor< u64, S2, IntConst<u64, (u64)1> > >, IntConst<u64, (u64)1> > >,
00306             PPC64SetF< D0, D2, IntSub< u64, S1, IntAdd< u64, S0, BitXor< u64, S2, IntConst<u64, (u64)1> > > > >     // lhs - (rhs+BO)
00307         >
00308     }}},
00309 
00310     {"addme",   MASK_X10FOE, OPCODE_X10FOE(31, 234, 0, 0), 1, {{OpClassCode::iALU,  { R0, CA, -1}, { R1, CA, -1, -1, -1, -1}, 
00311         Sequence2<
00312                   Set< D1,     CarryOfAddWithCarry< u64, S0, IntConst<u64, ~(u64)0>, S1 > >,
00313                   Set< D0,     IntAdd< u64, IntAdd< u64, S0, IntConst<u64, ~(u64)0> >, S1> >
00314         >
00315     }}},
00316     {"addme.",  MASK_X10FOE, OPCODE_X10FOE(31, 234, 0, 1), 1, {{OpClassCode::iALU,  { R0, CA,CR0}, { R1, CA, -1, -1, -1, -1}, 
00317         Sequence2<
00318                   Set< D1,     CarryOfAddWithCarry< u64, S0, IntConst<u64, ~(u64)0>, S1 > >,
00319             PPC64SetF< D0, D2, IntAdd< u64, IntAdd< u64, S0, IntConst<u64, ~(u64)0> >, S1> >
00320         >
00321     }}},
00322     {"subfme",  MASK_X10FOE, OPCODE_X10FOE(31, 232, 0, 0), 1, {{OpClassCode::iALU,  { R0, CA, -1}, { R1, CA, -1, -1, -1, -1}, 
00323         Sequence2<
00324                   Set< D1,     BitXor< u64, BorrowOfSubWithBorrow< u64, IntConst<u64, ~(u64)0>, S0, BitXor< u64, S1, IntConst<u64, (u64)1> > >, IntConst<u64, (u64)1> > >,
00325                   Set< D0,     IntSub< u64, IntConst<u64, ~(u64)0>, IntAdd< u64, S0, BitXor< u64, S1, IntConst<u64, (u64)1> > > > >     // lhs - (rhs+BO)
00326         >
00327     }}},
00328     {"subfme.", MASK_X10FOE, OPCODE_X10FOE(31, 232, 0, 1), 1, {{OpClassCode::iALU,  { R0, CA,CR0}, { R1, CA, -1, -1, -1, -1}, 
00329         Sequence2<
00330                   Set< D1,     BitXor< u64, BorrowOfSubWithBorrow< u64, IntConst<u64, ~(u64)0>, S0, BitXor< u64, S1, IntConst<u64, (u64)1> > >, IntConst<u64, (u64)1> > >,
00331             PPC64SetF< D0, D2, IntSub< u64, IntConst<u64, ~(u64)0>, IntAdd< u64, S0, BitXor< u64, S1, IntConst<u64, (u64)1> > > > >     // lhs - (rhs+BO)
00332         >
00333     }}},
00334 
00335     {"addze",   MASK_X10FOE, OPCODE_X10FOE(31, 202, 0, 0), 1, {{OpClassCode::iALU,  { R0, CA, -1}, { R1, CA, -1, -1, -1, -1}, 
00336         Sequence2<
00337                   Set< D1,     CarryOfAdd< u64, S0, S1 > >,
00338                   Set< D0,     IntAdd< u64, S0, S1 > >
00339         >
00340     }}},
00341     {"addze.",  MASK_X10FOE, OPCODE_X10FOE(31, 202, 0, 1), 1, {{OpClassCode::iALU,  { R0, CA,CR0}, { R1, CA, -1, -1, -1, -1}, 
00342         Sequence2<
00343                   Set< D1,     CarryOfAdd< u64, S0, S1 > >,
00344             PPC64SetF< D0, D2, IntAdd< u64, S0, S1 > >
00345         >
00346     }}},
00347     {"subfze",  MASK_X10FOE, OPCODE_X10FOE(31, 200, 0, 0), 1, {{OpClassCode::iALU,  { R0, CA, -1}, { R1, CA, -1, -1, -1, -1}, 
00348         Sequence2<
00349                   Set< D1,     BitXor< u64, BorrowOfSubWithBorrow< u64, IntConst<u64, 0>, S0, BitXor< u64, S1, IntConst<u64, (u64)1> > >, IntConst<u64, (u64)1> > >,
00350                   Set< D0,     IntSub< u64, IntConst<u64, 0>, IntAdd< u64, S0, BitXor< u64, S1, IntConst<u64, (u64)1> > > > >       // lhs - (rhs+BO)
00351         >
00352     }}},
00353     {"subfze.", MASK_X10FOE, OPCODE_X10FOE(31, 200, 0, 1), 1, {{OpClassCode::iALU,  { R0, CA,CR0}, { R1, CA, -1, -1, -1, -1}, 
00354         Sequence2<
00355                   Set< D1,     BitXor< u64, BorrowOfSubWithBorrow< u64, IntConst<u64, 0>, S0, BitXor< u64, S1, IntConst<u64, (u64)1> > >, IntConst<u64, (u64)1> > >,
00356             PPC64SetF< D0, D2, IntSub< u64, IntConst<u64, 0>, IntAdd< u64, S0, BitXor< u64, S1, IntConst<u64, (u64)1> > > > >       // lhs - (rhs+BO)
00357         >
00358     }}},
00359 
00360     {"neg",     MASK_X10FOE, OPCODE_X10FOE(31, 104, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, -1, -1, -1, -1, -1},       Set< D0,     IntNeg<u64, S0> >}}},
00361     {"neg.",    MASK_X10FOE, OPCODE_X10FOE(31, 104, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, -1, -1, -1, -1, -1}, PPC64SetF< D0, D1, IntNeg<u64, S0> >}}},
00362 
00363     {"mulli",   MASK_OP, OPCODE_OP(7), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1},       Set< D0,     IntMul< s64, S0, S1 > >}}},
00364 
00365     {"mullw",   MASK_X10FOE, OPCODE_X10FOE(31, 235, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1},       Set< D0,     IntMul< s64, Cast<s32, S0>, Cast<s32, S1> > >}}},
00366     {"mullw.",  MASK_X10FOE, OPCODE_X10FOE(31, 235, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, IntMul< s64, Cast<s32, S0>, Cast<s32, S1> > >}}},
00367 
00368     // AShiftR: dl32rbgundefinedCタ@ (PS3) g
00369     {"mulhw",   MASK_X10FOE, OPCODE_X10FOE(31,  75, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1},       Set< D0,     AShiftR< s64, IntMul< s64, Cast<s32, S0>, Cast<s32, S1> >, IntConst<unsigned int, 32>, 63 > >}}},
00370     {"mulhw.",  MASK_X10FOE, OPCODE_X10FOE(31,  75, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, AShiftR< s64, IntMul< s64, Cast<s32, S0>, Cast<s32, S1> >, IntConst<unsigned int, 32>, 63 > >}}},
00371 
00372     {"mulhwu",  MASK_X10FOE, OPCODE_X10FOE(31,  11, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1},       Set< D0,     LShiftR< u64, IntMul< u64, Cast<u32, S0>, Cast<u32, S1> >, IntConst<unsigned int, 32>, 63 > >}}},
00373     {"mulhwu.", MASK_X10FOE, OPCODE_X10FOE(31,  11, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, LShiftR< u64, IntMul< u64, Cast<u32, S0>, Cast<u32, S1> >, IntConst<unsigned int, 32>, 63 > >}}},
00374 
00375     {"divw",    MASK_X10FOE, OPCODE_X10FOE(31, 491, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1},       Set< D0,     IntDiv< s32, S0, S1 > >}}},
00376     {"divw.",   MASK_X10FOE, OPCODE_X10FOE(31, 491, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, IntDiv< s32, S0, S1 > >}}},
00377 
00378     {"divwu",   MASK_X10FOE, OPCODE_X10FOE(31, 459, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1},       Set< D0,     IntDiv< u32, S0, S1 > >}}},
00379     {"divwu.",  MASK_X10FOE, OPCODE_X10FOE(31, 459, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, IntDiv< u32, S0, S1 > >}}},
00380 
00381     {"mulld",   MASK_X10FOE, OPCODE_X10FOE(31, 233, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1},       Set< D0,     IntMul< s64, Cast<s64, S0>, Cast<s64, S1> > >}}},
00382     {"mulld.",  MASK_X10FOE, OPCODE_X10FOE(31, 233, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, IntMul< s64, Cast<s64, S0>, Cast<s64, S1> > >}}},
00383 
00384     {"mulhd",   MASK_X10FOE, OPCODE_X10FOE(31,  73, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1},       Set< D0,     IntSMulh64< S0, S1> >}}},
00385     {"mulhd.",  MASK_X10FOE, OPCODE_X10FOE(31,  73, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, IntSMulh64< S0, S1> >}}},
00386 
00387     {"mulhdu",  MASK_X10FOE, OPCODE_X10FOE(31,   9, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1},       Set< D0,     IntUMulh64< S0, S1> >}}},
00388     {"mulhdu.", MASK_X10FOE, OPCODE_X10FOE(31,   9, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, IntUMulh64< S0, S1> >}}},
00389 
00390     {"divd",    MASK_X10FOE, OPCODE_X10FOE(31, 489, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1},       Set< D0,     IntDiv< s64, S0, S1> >}}},
00391     {"divd.",   MASK_X10FOE, OPCODE_X10FOE(31, 489, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, IntDiv< s64, S0, S1> >}}},
00392 
00393     {"divdu",   MASK_X10FOE, OPCODE_X10FOE(31, 457, 0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1},       Set< D0,     IntDiv< u64, S0, S1> >}}},
00394     {"divdu.",  MASK_X10FOE, OPCODE_X10FOE(31, 457, 0, 1), 1, {{OpClassCode::iALU,  { R0,CR0, -1}, { R1, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, IntDiv< u64, S0, S1> >}}},
00395 
00396     // compare
00397     {"cmpwi",   MASK_DCMP, OPCODE_DCMP(11, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0, PPC64Compare< s32, S0, S1 > >}}},
00398     {"cmpdi",   MASK_DCMP, OPCODE_DCMP(11, 1), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0, PPC64Compare< s64, S0, S1 > >}}},
00399     {"cmpw",    MASK_X10CMP, OPCODE_X10CMP(31,   0, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0, PPC64Compare< s32, S0, S1 > >}}},
00400     {"cmpd",    MASK_X10CMP, OPCODE_X10CMP(31,   0, 1), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0, PPC64Compare< s64, S0, S1 > >}}},
00401 
00402     {"cmplwi",  MASK_DCMP, OPCODE_DCMP(10, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0, PPC64Compare< u32, S0, S1 > >}}},
00403     {"cmpldi",  MASK_DCMP, OPCODE_DCMP(10, 1), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0, PPC64Compare< u64, S0, S1 > >}}},
00404     {"cmplw",   MASK_X10CMP, OPCODE_X10CMP(31,  32, 0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0, PPC64Compare< u32, S0, S1 > >}}},
00405     {"cmpld",   MASK_X10CMP, OPCODE_X10CMP(31,  32, 1), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0, PPC64Compare< u64, S0, S1 > >}}},
00406 
00407     // logical
00408     {"andi.",   MASK_OP, OPCODE_OP(28), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, I0, -1, -1, -1, -1}, PPC64SetF< D0, D1, BitAnd< u64, S0, S1 > >}}},
00409     {"andis.",  MASK_OP, OPCODE_OP(29), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, I0, -1, -1, -1, -1}, PPC64SetF< D0, D1, BitAnd< u64, S0, LShiftL< u64, S1, IntConst<unsigned int,16>, 63> > >}}},
00410     {"ori",     MASK_OP, OPCODE_OP(24), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, I0, -1, -1, -1, -1}, Set< D0, BitOr< u64, S0, S1 > >}}},
00411     {"oris",    MASK_OP, OPCODE_OP(25), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, I0, -1, -1, -1, -1}, Set< D0, BitOr< u64, S0, LShiftL< u64, S1, IntConst<unsigned int,16>, 63> > >}}},
00412     {"xori",    MASK_OP, OPCODE_OP(26), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, I0, -1, -1, -1, -1}, Set< D0, BitXor< u64, S0, S1 > >}}},
00413     {"xoris",   MASK_OP, OPCODE_OP(27), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, I0, -1, -1, -1, -1}, Set< D0, BitXor< u64, S0, LShiftL< u64, S1, IntConst<unsigned int,16>, 63> > >}}},
00414 
00415     {"and",     MASK_X10F, OPCODE_X10F(31,  28, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, R2, -1, -1, -1, -1},       Set< D0,     BitAnd< u64, S0, S1 > >}}},
00416     {"and.",    MASK_X10F, OPCODE_X10F(31,  28, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, BitAnd< u64, S0, S1 > >}}},
00417     {"or",      MASK_X10F, OPCODE_X10F(31, 444, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, R2, -1, -1, -1, -1},       Set< D0,     BitOr< u64, S0, S1 > >}}},
00418     {"or.",     MASK_X10F, OPCODE_X10F(31, 444, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, BitOr< u64, S0, S1 > >}}},
00419     {"xor",     MASK_X10F, OPCODE_X10F(31, 316, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, R2, -1, -1, -1, -1},       Set< D0,     BitXor< u64, S0, S1 > >}}},
00420     {"xor.",    MASK_X10F, OPCODE_X10F(31, 316, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, BitXor< u64, S0, S1 > >}}},
00421     {"nand",    MASK_X10F, OPCODE_X10F(31, 476, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, R2, -1, -1, -1, -1},       Set< D0,     BitNand< u64, S0, S1 > >}}},
00422     {"nand.",   MASK_X10F, OPCODE_X10F(31, 476, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, BitNand< u64, S0, S1 > >}}},
00423     {"nor",     MASK_X10F, OPCODE_X10F(31, 124, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, R2, -1, -1, -1, -1},       Set< D0,     BitNor< u64, S0, S1 > >}}},
00424     {"nor.",    MASK_X10F, OPCODE_X10F(31, 124, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, BitNor< u64, S0, S1 > >}}},
00425     {"eqv",     MASK_X10F, OPCODE_X10F(31, 284, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, R2, -1, -1, -1, -1},       Set< D0,     BitXorNot< u64, S0, S1 > >}}},
00426     {"eqv.",    MASK_X10F, OPCODE_X10F(31, 284, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, BitXorNot< u64, S0, S1 > >}}},
00427     {"andc",    MASK_X10F, OPCODE_X10F(31,  60, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, R2, -1, -1, -1, -1},       Set< D0,     BitAndNot< u64, S0, S1 > >}}},
00428     {"andc.",   MASK_X10F, OPCODE_X10F(31,  60, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, BitAndNot< u64, S0, S1 > >}}},
00429     {"orc",     MASK_X10F, OPCODE_X10F(31, 412, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, R2, -1, -1, -1, -1},       Set< D0,     BitOrNot< u64, S0, S1 > >}}},
00430     {"orc.",    MASK_X10F, OPCODE_X10F(31, 412, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, BitOrNot< u64, S0, S1 > >}}},
00431     
00432     {"extsb",   MASK_X10F, OPCODE_X10F(31, 954, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, -1, -1, -1, -1, -1},       SetSext< D0,     Cast< u8, S0 > >}}},
00433     {"extsb.",  MASK_X10F, OPCODE_X10F(31, 954, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, -1, -1, -1, -1, -1}, PPC64SetSextF< D0, D1, Cast< u8, S0 > >}}},
00434     {"extsh",   MASK_X10F, OPCODE_X10F(31, 922, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, -1, -1, -1, -1, -1},       SetSext< D0,     Cast< u16, S0 > >}}},
00435     {"extsh.",  MASK_X10F, OPCODE_X10F(31, 922, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, -1, -1, -1, -1, -1}, PPC64SetSextF< D0, D1, Cast< u16, S0 > >}}},
00436     {"extsw",   MASK_X10F, OPCODE_X10F(31, 986, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, -1, -1, -1, -1, -1},       SetSext< D0,     Cast< u32, S0 > >}}},
00437     {"extsw.",  MASK_X10F, OPCODE_X10F(31, 986, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, -1, -1, -1, -1, -1}, PPC64SetSextF< D0, D1, Cast< u32, S0 > >}}},
00438     
00439     {"cntlzw",  MASK_X10F, OPCODE_X10F(31,  26, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, -1, -1, -1, -1, -1},       Set< D0,     PPC64Cntlz< u32, S0 > >}}},
00440     {"cntlzw.", MASK_X10F, OPCODE_X10F(31,  26, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, -1, -1, -1, -1, -1}, PPC64SetF< D0, D1, PPC64Cntlz< u32, S0 > >}}},
00441     {"cntlzd",  MASK_X10F, OPCODE_X10F(31,  58, 0), 1, {{OpClassCode::iALU,  { R1, -1, -1}, { R0, -1, -1, -1, -1, -1},       Set< D0,     PPC64Cntlz< u64, S0 > >}}},
00442     {"cntlzd.", MASK_X10F, OPCODE_X10F(31,  58, 1), 1, {{OpClassCode::iALU,  { R1,CR0, -1}, { R0, -1, -1, -1, -1, -1}, PPC64SetF< D0, D1, PPC64Cntlz< u64, S0 > >}}},
00443 
00444     // rotate
00445     {"rlwinm",  MASK_OPF, OPCODE_OPF(21, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, I0, I1, I2, -1, -1},       Set< D0,     PPC64Mask< u32, RotateL<u32, S0, S1>, S2, S3 > >}}},
00446     {"rlwinm.", MASK_OPF, OPCODE_OPF(21, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, I0, I1, I2, -1, -1}, PPC64SetF< D0, D1, PPC64Mask< u32, RotateL<u32, S0, S1>,  S2, S3 > >}}},
00447     {"rlwnm",   MASK_OPF, OPCODE_OPF(23, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, R2, I0, I1, -1, -1},       Set< D0,     PPC64Mask< u32, RotateL<u32, S0, S1>, S2, S3 > >}}},
00448     {"rlwnm.",  MASK_OPF, OPCODE_OPF(23, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, R2, I0, I1, -1, -1}, PPC64SetF< D0, D1, PPC64Mask< u32, RotateL<u32, S0, S1>, S2, S3 > >}}},
00449     {"rlwimi",  MASK_OPF, OPCODE_OPF(20, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, R1, I0, I1, I2, -1},       Set< D0,     PPC64MaskInsert< u32, S1, RotateL<u32, S0, S2>, S3, S4 > >}}},
00450     {"rlwimi.", MASK_OPF, OPCODE_OPF(20, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, R1, I0, I1, I2, -1}, PPC64SetF< D0, D1, PPC64MaskInsert< u32, S1, RotateL<u32, S0, S2>, S3, S4 > >}}},
00451 
00452     {"rldicl",  MASK_MD, OPCODE_MD(30, 0, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, I0, I1, -1, -1, -1},       Set< D0,     PPC64Mask< u64, RotateL<u64, S0, S1>, S2, IntConst<unsigned int, 63> > >}}},
00453     {"rldicl.", MASK_MD, OPCODE_MD(30, 0, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, I0, I1, -1, -1, -1}, PPC64SetF< D0, D1, PPC64Mask< u64, RotateL<u64, S0, S1>, S2, IntConst<unsigned int, 63> > >}}},
00454     {"rldicr",  MASK_MD, OPCODE_MD(30, 1, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, I0, I1, -1, -1, -1},       Set< D0,     PPC64Mask< u64, RotateL<u64, S0, S1>, IntConst<unsigned int, 0>, S2 > >}}},
00455     {"rldicr.", MASK_MD, OPCODE_MD(30, 1, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, I0, I1, -1, -1, -1}, PPC64SetF< D0, D1, PPC64Mask< u64, RotateL<u64, S0, S1>, IntConst<unsigned int, 0>, S2 > >}}},
00456     {"rldic",   MASK_MD, OPCODE_MD(30, 2, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, I0, I1, -1, -1, -1},       Set< D0,     PPC64Mask< u64, RotateL<u64, S0, S1>, S2, BitNot<u64, S1> > >}}},
00457     {"rldic.",  MASK_MD, OPCODE_MD(30, 2, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, I0, I1, -1, -1, -1}, PPC64SetF< D0, D1, PPC64Mask< u64, RotateL<u64, S0, S1>, S2, BitNot<u64, S1> > >}}},
00458 
00459     {"rldimi",  MASK_MD, OPCODE_MD(30, 3, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, R1, I0, I1, -1, -1},       Set< D0,     PPC64MaskInsert< u64, S1, RotateL<u64, S0, S2>, S3, BitNot<u64, S2> > >}}},
00460     {"rldimi.", MASK_MD, OPCODE_MD(30, 3, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, R1, I0, I1, -1, -1}, PPC64SetF< D0, D1, PPC64MaskInsert< u64, S1, RotateL<u64, S0, S2>, S3, BitNot<u64, S2> > >}}},
00461 
00462     {"rldcl",   MASK_MDS, OPCODE_MDS(30, 8, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, R1, I0, -1, -1, -1},       Set< D0,     PPC64Mask< u64, RotateL<u64, S0, S1>, S2, IntConst<unsigned int, 63> > >}}},
00463     {"rldcl.",  MASK_MDS, OPCODE_MDS(30, 8, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, R1, I0, -1, -1, -1}, PPC64SetF< D0, D1, PPC64Mask< u64, RotateL<u64, S0, S1>, S2, IntConst<unsigned int, 63> > >}}},
00464     {"rldcr",   MASK_MDS, OPCODE_MDS(30, 9, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, R1, I0, -1, -1, -1},       Set< D0,     PPC64Mask< u64, RotateL<u64, S0, S1>, IntConst<unsigned int, 0>, S2 > >}}},
00465     {"rldcr.",  MASK_MDS, OPCODE_MDS(30, 9, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, R1, I0, -1, -1, -1}, PPC64SetF< D0, D1, PPC64Mask< u64, RotateL<u64, S0, S1>, IntConst<unsigned int, 0>, S2 > >}}},
00466 
00467     // shift
00468     {"slw",     MASK_X10F, OPCODE_X10F(31,  24, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, R2, -1, -1, -1, -1},       Set< D0,     LShiftL<u32, S0, S1, 0x3f> >}}},
00469     {"slw.",    MASK_X10F, OPCODE_X10F(31,  24, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, LShiftL<u32, S0, S1, 0x3f> >}}},
00470     {"srw",     MASK_X10F, OPCODE_X10F(31, 536, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, R2, -1, -1, -1, -1},       Set< D0,     LShiftR<u32, S0, S1, 0x3f> >}}},
00471     {"srw.",    MASK_X10F, OPCODE_X10F(31, 536, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, LShiftR<u32, S0, S1, 0x3f> >}}},
00472 
00473     {"srawi",   MASK_X10F, OPCODE_X10F(31, 824, 0), 1, {{OpClassCode::iSFT,  { R1, CA, -1}, { R0, I0, -1, -1, -1, -1},
00474         Sequence2<
00475                       Set< D1,     PPC64CarryOfAShiftR<u32, S0, S1, 0x3f> >,
00476                   SetSext< D0,     AShiftR<u32, S0, S1, 0x3f> >
00477         >
00478     }}},
00479     {"srawi.",  MASK_X10F, OPCODE_X10F(31, 824, 1), 1, {{OpClassCode::iSFT,  { R1, CA,CR0}, { R0, I0, -1, -1, -1, -1},
00480         Sequence2<
00481                       Set< D1,     PPC64CarryOfAShiftR<u32, S0, S1, 0x3f> >,
00482             PPC64SetSextF< D0, D2, AShiftR<u32, S0, S1, 0x3f> >
00483         >
00484     }}},
00485     {"sraw",    MASK_X10F, OPCODE_X10F(31, 792, 0), 1, {{OpClassCode::iSFT,  { R1, CA, -1}, { R0, R2, -1, -1, -1, -1},
00486         Sequence2<
00487                       Set< D1,     PPC64CarryOfAShiftR<u32, S0, S1, 0x3f> >,
00488                   SetSext< D0,     AShiftR<u32, S0, S1, 0x3f> >
00489         >
00490     }}},
00491     {"sraw.",   MASK_X10F, OPCODE_X10F(31, 792, 1), 1, {{OpClassCode::iSFT,  { R1, CA,CR0}, { R0, R2, -1, -1, -1, -1},
00492         Sequence2<
00493                       Set< D1,     PPC64CarryOfAShiftR<u32, S0, S1, 0x3f> >,
00494             PPC64SetSextF< D0, D2, AShiftR<u32, S0, S1, 0x3f> >
00495         >
00496     }}},
00497     {"sld",     MASK_X10F, OPCODE_X10F(31,  27, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, R2, -1, -1, -1, -1},       Set< D0,     LShiftL<u64, S0, S1, 0x7f> >}}},
00498     {"sld.",    MASK_X10F, OPCODE_X10F(31,  27, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, LShiftL<u64, S0, S1, 0x7f> >}}},
00499     {"srd",     MASK_X10F, OPCODE_X10F(31, 539, 0), 1, {{OpClassCode::iSFT,  { R1, -1, -1}, { R0, R2, -1, -1, -1, -1},       Set< D0,     LShiftR<u64, S0, S1, 0x7f> >}}},
00500     {"srd.",    MASK_X10F, OPCODE_X10F(31, 539, 1), 1, {{OpClassCode::iSFT,  { R1,CR0, -1}, { R0, R2, -1, -1, -1, -1}, PPC64SetF< D0, D1, LShiftR<u64, S0, S1, 0x7f> >}}},
00501 
00502     {"sradi",   MASK_X10FSH, OPCODE_X10F(31, 826, 0), 1, {{OpClassCode::iSFT,  { R1, CA, -1}, { R0, I0, -1, -1, -1, -1},
00503         Sequence2<
00504                   Set< D1,     PPC64CarryOfAShiftR<u64, S0, S1, 0x7f> >,
00505                   Set< D0,     AShiftR<u64, S0, S1, 0x7f> >
00506         >
00507     }}},
00508     {"sradi.",  MASK_X10FSH, OPCODE_X10F(31, 826, 1), 1, {{OpClassCode::iSFT,  { R1, CA,CR0}, { R0, I0, -1, -1, -1, -1},
00509         Sequence2<
00510                   Set< D1,     PPC64CarryOfAShiftR<u64, S0, S1, 0x7f> >,
00511             PPC64SetF< D0, D2, AShiftR<u64, S0, S1, 0x7f> >
00512         >
00513     }}},
00514     {"srad",    MASK_X10F, OPCODE_X10F(31, 794, 0), 1, {{OpClassCode::iSFT,  { R1, CA, -1}, { R0, R2, -1, -1, -1, -1},
00515         Sequence2<
00516                   Set< D1,     PPC64CarryOfAShiftR<u64, S0, S1, 0x7f> >,
00517                   Set< D0,     AShiftR<u64, S0, S1, 0x7f> >
00518         >
00519     }}},
00520     {"srad.",   MASK_X10F, OPCODE_X10F(31, 794, 1), 1, {{OpClassCode::iSFT,  { R1, CA,CR0}, { R0, R2, -1, -1, -1, -1},
00521         Sequence2<
00522                   Set< D1,     PPC64CarryOfAShiftR<u64, S0, S1, 0x7f> >,
00523             PPC64SetF< D0, D2, AShiftR<u64, S0, S1, 0x7f> >
00524         >
00525     }}},
00526 
00527 
00528     // mtspr/mfspr
00529 
00530     {"mtlr",    MASK_MTFSPR, OPCODE_MTFSPR(31, 467, 8), 1, {{OpClassCode::iALU,  { LR, -1, -1}, { R0, -1, -1, -1 -1, -1}, Set< D0, S0 >}}},
00531     {"mtctr",   MASK_MTFSPR, OPCODE_MTFSPR(31, 467, 9), 1, {{OpClassCode::iALU,  {CTR, -1, -1}, { R0, -1, -1, -1 -1, -1}, Set< D0, S0 >}}},
00532     {"mflr",    MASK_MTFSPR, OPCODE_MTFSPR(31, 339, 8), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { LR, -1, -1, -1 -1, -1}, Set< D0, S0 >}}},
00533     {"mfctr",   MASK_MTFSPR, OPCODE_MTFSPR(31, 339, 9), 1, {{OpClassCode::iALU,  { R0, -1, -1}, {CTR, -1, -1, -1 -1, -1}, Set< D0, S0 >}}},
00534 
00535     // move from time base : タ
00536     {"mftb",    MASK_MTFSPR, OPCODE_MTFSPR(31, 371, 268), 1, {{OpClassCode::iMOV,  { R0, -1, -1}, { -1, -1, -1, -1, -1, -1}, Set< D0, IntConst<u64, 0> >}}},
00537     {"mftbu",   MASK_MTFSPR, OPCODE_MTFSPR(31, 371, 269), 1, {{OpClassCode::iMOV,  { R0, -1, -1}, { -1, -1, -1, -1, -1, -1}, Set< D0, IntConst<u64, 0> >}}},
00538 
00539     // condition register
00540 
00541     // Cmtcrf 1CRST|[g
00542     {"mtcrf",   MASK_MTCRF, OPCODE_MTCRF(31, 144, 0x01), 1, {{OpClassCode::iALU,  {CR7, -1, -1}, { R0, -1, -1, -1 -1, -1}, Set< D0, BitExtract< u64, S0, IntConst<unsigned int,  0>, IntConst<unsigned int, 4> > >}}},
00543     {"mtcrf",   MASK_MTCRF, OPCODE_MTCRF(31, 144, 0x02), 1, {{OpClassCode::iALU,  {CR6, -1, -1}, { R0, -1, -1, -1 -1, -1}, Set< D0, BitExtract< u64, S0, IntConst<unsigned int,  4>, IntConst<unsigned int, 4> > >}}},
00544     {"mtcrf",   MASK_MTCRF, OPCODE_MTCRF(31, 144, 0x04), 1, {{OpClassCode::iALU,  {CR5, -1, -1}, { R0, -1, -1, -1 -1, -1}, Set< D0, BitExtract< u64, S0, IntConst<unsigned int,  8>, IntConst<unsigned int, 4> > >}}},
00545     {"mtcrf",   MASK_MTCRF, OPCODE_MTCRF(31, 144, 0x08), 1, {{OpClassCode::iALU,  {CR4, -1, -1}, { R0, -1, -1, -1 -1, -1}, Set< D0, BitExtract< u64, S0, IntConst<unsigned int, 12>, IntConst<unsigned int, 4> > >}}},
00546     {"mtcrf",   MASK_MTCRF, OPCODE_MTCRF(31, 144, 0x10), 1, {{OpClassCode::iALU,  {CR3, -1, -1}, { R0, -1, -1, -1 -1, -1}, Set< D0, BitExtract< u64, S0, IntConst<unsigned int, 16>, IntConst<unsigned int, 4> > >}}},
00547     {"mtcrf",   MASK_MTCRF, OPCODE_MTCRF(31, 144, 0x20), 1, {{OpClassCode::iALU,  {CR2, -1, -1}, { R0, -1, -1, -1 -1, -1}, Set< D0, BitExtract< u64, S0, IntConst<unsigned int, 20>, IntConst<unsigned int, 4> > >}}},
00548     {"mtcrf",   MASK_MTCRF, OPCODE_MTCRF(31, 144, 0x40), 1, {{OpClassCode::iALU,  {CR1, -1, -1}, { R0, -1, -1, -1 -1, -1}, Set< D0, BitExtract< u64, S0, IntConst<unsigned int, 24>, IntConst<unsigned int, 4> > >}}},
00549     {"mtcrf",   MASK_MTCRF, OPCODE_MTCRF(31, 144, 0x80), 1, {{OpClassCode::iALU,  {CR0, -1, -1}, { R0, -1, -1, -1 -1, -1}, Set< D0, BitExtract< u64, S0, IntConst<unsigned int, 28>, IntConst<unsigned int, 4> > >}}},
00550     
00551     {"mtcr",    MASK_MTCRF, OPCODE_MTCRF(31, 144, 0xff), 3, {
00552         {OpClassCode::iALU,  {CR0,CR1,CR2}, { R0, -1, -1,  -1 -1, -1}, 
00553             Sequence3<
00554                 Set< D0, BitExtract< u64, S0, IntConst<unsigned int, 28>, IntConst<unsigned int, 4> > >, 
00555                 Set< D1, BitExtract< u64, S0, IntConst<unsigned int, 24>, IntConst<unsigned int, 4> > >, 
00556                 Set< D2, BitExtract< u64, S0, IntConst<unsigned int, 20>, IntConst<unsigned int, 4> > >
00557             >}, 
00558         {OpClassCode::iALU,  {CR3,CR4,CR5}, { R0, -1, -1,  -1 -1, -1}, 
00559             Sequence3<
00560                 Set< D0, BitExtract< u64, S0, IntConst<unsigned int, 16>, IntConst<unsigned int, 4> > >, 
00561                 Set< D1, BitExtract< u64, S0, IntConst<unsigned int, 12>, IntConst<unsigned int, 4> > >, 
00562                 Set< D2, BitExtract< u64, S0, IntConst<unsigned int,  8>, IntConst<unsigned int, 4> > >
00563             >}, 
00564         {OpClassCode::iALU,  {CR6,CR7, -1}, { R0, -1, -1,  -1 -1, -1}, 
00565             Sequence2<
00566                 Set< D0, BitExtract< u64, S0, IntConst<unsigned int,  4>, IntConst<unsigned int, 4> > >, 
00567                 Set< D1, BitExtract< u64, S0, IntConst<unsigned int,  0>, IntConst<unsigned int, 4> > >
00568             >}, 
00569     }},
00570 
00571     {"mfcr",    MASK_X10|0x00100000, OPCODE_X10(31,  19), 3, {
00572         {OpClassCode::iALU,  { R0, -1, -1}, {CR0,CR1,CR2,CR3, -1, -1}, 
00573             Set< D0, BitOr< u64, BitOr< u64, BitOr< u64, 
00574                 LShiftL<u64, S0, IntConst<unsigned int, 28>, 63 >, 
00575                 LShiftL<u64, S1, IntConst<unsigned int, 24>, 63 > >, 
00576                 LShiftL<u64, S2, IntConst<unsigned int, 20>, 63 > >, 
00577                 LShiftL<u64, S3, IntConst<unsigned int, 16>, 63 > > >, 
00578         },
00579         {OpClassCode::iALU,  { R0, -1, -1}, {CR4,CR5, R0, -1, -1, -1}, 
00580             Set< D0, BitOr< u64, BitOr< u64,
00581                 S2,
00582                 LShiftL<u64, S0, IntConst<unsigned int, 12>, 63 > >, 
00583                 LShiftL<u64, S1, IntConst<unsigned int,  8>, 63 > > >, 
00584         },
00585         {OpClassCode::iALU,  { R0, -1, -1}, {CR6,CR7, R0, -1, -1, -1}, 
00586             Set< D0, BitOr< u64, BitOr< u64, 
00587                 S2,
00588                 LShiftL<u64, S0, IntConst<unsigned int,  4>, 63 > >, 
00589                 LShiftL<u64, S1, IntConst<unsigned int,  0>, 63 > > >, 
00590         },
00591     }},
00592 
00593 
00594 
00595 
00596     //
00597     // FP instructions
00598     //
00599     // FX (FPSCR[32]) T|[gDFPタsD
00600 
00601     // move
00602     {"fmr",     MASK_X10F, OPCODE_X10F(63,  72, 0), 1, {{OpClassCode::fMOV,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},         Set< D0,         S1 >}}},
00603     {"fmr.",    MASK_X10F, OPCODE_X10F(63,  72, 1), 1, {{OpClassCode::fMOV,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, SD1 >}}},
00604 
00605     {"fneg",    MASK_X10F, OPCODE_X10F(63,  40, 0), 1, {{OpClassCode::fNEG,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         FPNeg< double, SD1 > >}}},
00606     {"fneg.",   MASK_X10F, OPCODE_X10F(63,  40, 1), 1, {{OpClassCode::fNEG,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, FPNeg< double, SD1 > >}}},
00607 
00608     {"fabs",    MASK_X10F, OPCODE_X10F(63, 264, 0), 1, {{OpClassCode::fNEG,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         FPAbs< double, SD1 > >}}},
00609     {"fabs.",   MASK_X10F, OPCODE_X10F(63, 264, 1), 1, {{OpClassCode::fNEG,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, FPAbs< double, SD1 > >}}},
00610 
00611     {"fnabs",   MASK_X10F, OPCODE_X10F(63, 136, 0), 1, {{OpClassCode::fNEG,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         FPNeg< double, FPAbs<double, SD1> > >}}},
00612     {"fnabs.",  MASK_X10F, OPCODE_X10F(63, 136, 1), 1, {{OpClassCode::fNEG,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, FPNeg< double, FPAbs<double, SD1> > >}}},
00613 
00614     // arithmetic
00615     {"fadd",    MASK_X5F, OPCODE_X5F(63,  21, 0), 1, {{OpClassCode::fADD,  { R0, -1, -1}, {FPC, R1, R2, -1, -1, -1},       SetFP< D0,                       FPAdd< double, SD1, SD2, PPC64FPSCRRoundMode<S0> > >}}},
00616     {"fadd.",   MASK_X5F, OPCODE_X5F(63,  21, 1), 1, {{OpClassCode::fADD,  { R0,CR1, -1}, {FPC, R1, R2, -1, -1, -1}, PPC64SetFPF< D0, D1, S0,               FPAdd< double, SD1, SD2, PPC64FPSCRRoundMode<S0> > >}}},
00617     {"fadds",   MASK_X5F, OPCODE_X5F(59,  21, 0), 1, {{OpClassCode::fADD,  { R0, -1, -1}, {FPC, R1, R2, -1, -1, -1},       SetFP< D0,         Cast< double, FPAdd<  float, SF1, SF2, PPC64FPSCRRoundMode<S0> > > >}}},
00618     {"fadds.",  MASK_X5F, OPCODE_X5F(59,  21, 1), 1, {{OpClassCode::fADD,  { R0,CR1, -1}, {FPC, R1, R2, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< double, FPAdd<  float, SF1, SF2, PPC64FPSCRRoundMode<S0> > > >}}},
00619 
00620     {"fsub",    MASK_X5F, OPCODE_X5F(63,  20, 0), 1, {{OpClassCode::fADD,  { R0, -1, -1}, {FPC, R1, R2, -1, -1, -1},       SetFP< D0,                       FPSub< double, SD1, SD2, PPC64FPSCRRoundMode<S0> > >}}},
00621     {"fsub.",   MASK_X5F, OPCODE_X5F(63,  20, 1), 1, {{OpClassCode::fADD,  { R0,CR1, -1}, {FPC, R1, R2, -1, -1, -1}, PPC64SetFPF< D0, D1, S0,               FPSub< double, SD1, SD2, PPC64FPSCRRoundMode<S0> > >}}},
00622     {"fsubs",   MASK_X5F, OPCODE_X5F(59,  20, 0), 1, {{OpClassCode::fADD,  { R0, -1, -1}, {FPC, R1, R2, -1, -1, -1},       SetFP< D0,         Cast< double, FPSub<  float, SF1, SF2, PPC64FPSCRRoundMode<S0> > > >}}},
00623     {"fsubs.",  MASK_X5F, OPCODE_X5F(59,  20, 1), 1, {{OpClassCode::fADD,  { R0,CR1, -1}, {FPC, R1, R2, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< double, FPSub<  float, SF1, SF2, PPC64FPSCRRoundMode<S0> > > >}}},
00624 
00625     {"fmul",    MASK_X5F, OPCODE_X5F(63,  25, 0), 1, {{OpClassCode::fMUL,  { R0, -1, -1}, {FPC, R1, R2, -1, -1, -1},       SetFP< D0,                       FPMul< double, SD1, SD2, PPC64FPSCRRoundMode<S0> > >}}},
00626     {"fmul.",   MASK_X5F, OPCODE_X5F(63,  25, 1), 1, {{OpClassCode::fMUL,  { R0,CR1, -1}, {FPC, R1, R2, -1, -1, -1}, PPC64SetFPF< D0, D1, S0,               FPMul< double, SD1, SD2, PPC64FPSCRRoundMode<S0> > >}}},
00627     {"fmuls",   MASK_X5F, OPCODE_X5F(59,  25, 0), 1, {{OpClassCode::fMUL,  { R0, -1, -1}, {FPC, R1, R2, -1, -1, -1},       SetFP< D0,         Cast< double, FPMul<  float, SF1, SF2, PPC64FPSCRRoundMode<S0> > > >}}},
00628     {"fmuls.",  MASK_X5F, OPCODE_X5F(59,  25, 1), 1, {{OpClassCode::fMUL,  { R0,CR1, -1}, {FPC, R1, R2, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< double, FPMul<  float, SF1, SF2, PPC64FPSCRRoundMode<S0> > > >}}},
00629 
00630     {"fdiv",    MASK_X5F, OPCODE_X5F(63,  18, 0), 1, {{OpClassCode::fDIV,  { R0, -1, -1}, {FPC, R1, R2, -1, -1, -1},       SetFP< D0,                       FPDiv< double, SD1, SD2, PPC64FPSCRRoundMode<S0> > >}}},
00631     {"fdiv.",   MASK_X5F, OPCODE_X5F(63,  18, 1), 1, {{OpClassCode::fDIV,  { R0,CR1, -1}, {FPC, R1, R2, -1, -1, -1}, PPC64SetFPF< D0, D1, S0,               FPDiv< double, SD1, SD2, PPC64FPSCRRoundMode<S0> > >}}},
00632     {"fdivs",   MASK_X5F, OPCODE_X5F(59,  18, 0), 1, {{OpClassCode::fDIV,  { R0, -1, -1}, {FPC, R1, R2, -1, -1, -1},       SetFP< D0,         Cast< double, FPDiv<  float, SF1, SF2, PPC64FPSCRRoundMode<S0> > > >}}},
00633     {"fdivs.",  MASK_X5F, OPCODE_X5F(59,  18, 1), 1, {{OpClassCode::fDIV,  { R0,CR1, -1}, {FPC, R1, R2, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< double, FPDiv<  float, SF1, SF2, PPC64FPSCRRoundMode<S0> > > >}}},
00634 
00635     {"fsqrt",   MASK_X5F, OPCODE_X5F(63,  22, 0), 1, {{OpClassCode::fELEM, { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,                       FPSqrt< double, SD1, PPC64FPSCRRoundMode<S0> > >}}},
00636     {"fsqrt.",  MASK_X5F, OPCODE_X5F(63,  22, 1), 1, {{OpClassCode::fELEM, { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0,               FPSqrt< double, SD1, PPC64FPSCRRoundMode<S0> > >}}},
00637     {"fsqrts",  MASK_X5F, OPCODE_X5F(59,  22, 0), 1, {{OpClassCode::fELEM, { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         Cast< double, FPSqrt<  float, SF1, PPC64FPSCRRoundMode<S0> > > >}}},
00638     {"fsqrts.", MASK_X5F, OPCODE_X5F(59,  22, 1), 1, {{OpClassCode::fELEM, { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< double, FPSqrt<  float, SF1, PPC64FPSCRRoundMode<S0> > > >}}},
00639 
00640     //fre
00641     //fsqrtre
00642 
00643     //  OpClassCode H
00644     {"fmadd",   MASK_X5F, OPCODE_X5F(63,  29, 0), 1, {{OpClassCode::fMUL,  { R0, -1, -1}, {FPC, R1, R2, R3, -1, -1},       SetFP< D0,                       FPAdd< double, FPMul< double, SD1, SD3, PPC64FPSCRRoundMode<S0> >, SD2, PPC64FPSCRRoundMode<S0> > >}}},
00645     {"fmadd.",  MASK_X5F, OPCODE_X5F(63,  29, 1), 1, {{OpClassCode::fMUL,  { R0,CR1, -1}, {FPC, R1, R2, R3, -1, -1}, PPC64SetFPF< D0, D1, S0,               FPAdd< double, FPMul< double, SD1, SD3, PPC64FPSCRRoundMode<S0> >, SD2, PPC64FPSCRRoundMode<S0> > >}}},
00646     {"fmadds",  MASK_X5F, OPCODE_X5F(59,  29, 0), 1, {{OpClassCode::fMUL,  { R0, -1, -1}, {FPC, R1, R2, R3, -1, -1},       SetFP< D0,         Cast< double, FPAdd<  float, FPMul<  float, SF1, SF3, PPC64FPSCRRoundMode<S0> >, SF2, PPC64FPSCRRoundMode<S0> > > >}}},
00647     {"fmadds.", MASK_X5F, OPCODE_X5F(59,  29, 1), 1, {{OpClassCode::fMUL,  { R0,CR1, -1}, {FPC, R1, R2, R3, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< double, FPAdd<  float, FPMul<  float, SF1, SF3, PPC64FPSCRRoundMode<S0> >, SF2, PPC64FPSCRRoundMode<S0> > > >}}},
00648 
00649     {"fmsub",   MASK_X5F, OPCODE_X5F(63,  28, 0), 1, {{OpClassCode::fMUL,  { R0, -1, -1}, {FPC, R1, R2, R3, -1, -1},       SetFP< D0,                       FPSub< double, FPMul< double, SD1, SD3, PPC64FPSCRRoundMode<S0> >, SD2, PPC64FPSCRRoundMode<S0> > >}}},
00650     {"fmsub.",  MASK_X5F, OPCODE_X5F(63,  28, 1), 1, {{OpClassCode::fMUL,  { R0,CR1, -1}, {FPC, R1, R2, R3, -1, -1}, PPC64SetFPF< D0, D1, S0,               FPSub< double, FPMul< double, SD1, SD3, PPC64FPSCRRoundMode<S0> >, SD2, PPC64FPSCRRoundMode<S0> > >}}},
00651     {"fmsubs",  MASK_X5F, OPCODE_X5F(59,  28, 0), 1, {{OpClassCode::fMUL,  { R0, -1, -1}, {FPC, R1, R2, R3, -1, -1},       SetFP< D0,         Cast< double, FPSub<  float, FPMul<  float, SF1, SF3, PPC64FPSCRRoundMode<S0> >, SF2, PPC64FPSCRRoundMode<S0> > > >}}},
00652     {"fmsubs.", MASK_X5F, OPCODE_X5F(59,  28, 1), 1, {{OpClassCode::fMUL,  { R0,CR1, -1}, {FPC, R1, R2, R3, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< double, FPSub<  float, FPMul<  float, SF1, SF3, PPC64FPSCRRoundMode<S0> >, SF2, PPC64FPSCRRoundMode<S0> > > >}}},
00653 
00654     {"fnmadd",  MASK_X5F, OPCODE_X5F(63,  31, 0), 1, {{OpClassCode::fMUL,  { R0, -1, -1}, {FPC, R1, R2, R3, -1, -1},       SetFP< D0,                       FPNeg< double, FPAdd< double, FPMul< double, SD1, SD3, PPC64FPSCRRoundMode<S0> >, SD2, PPC64FPSCRRoundMode<S0> > > >}}},
00655     {"fnmadd.", MASK_X5F, OPCODE_X5F(63,  31, 1), 1, {{OpClassCode::fMUL,  { R0,CR1, -1}, {FPC, R1, R2, R3, -1, -1}, PPC64SetFPF< D0, D1, S0,               FPNeg< double, FPAdd< double, FPMul< double, SD1, SD3, PPC64FPSCRRoundMode<S0> >, SD2, PPC64FPSCRRoundMode<S0> > > >}}},
00656     {"fnmadds", MASK_X5F, OPCODE_X5F(59,  31, 0), 1, {{OpClassCode::fMUL,  { R0, -1, -1}, {FPC, R1, R2, R3, -1, -1},       SetFP< D0,         Cast< double, FPNeg<  float, FPAdd<  float, FPMul<  float, SF1, SF3, PPC64FPSCRRoundMode<S0> >, SF2, PPC64FPSCRRoundMode<S0> > > > >}}},
00657     {"fnmadds.",MASK_X5F, OPCODE_X5F(59,  31, 1), 1, {{OpClassCode::fMUL,  { R0,CR1, -1}, {FPC, R1, R2, R3, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< double, FPNeg<  float, FPAdd<  float, FPMul<  float, SF1, SF3, PPC64FPSCRRoundMode<S0> >, SF2, PPC64FPSCRRoundMode<S0> > > > >}}},
00658 
00659     {"fnmsub",  MASK_X5F, OPCODE_X5F(63,  30, 0), 1, {{OpClassCode::fMUL,  { R0, -1, -1}, {FPC, R1, R2, R3, -1, -1},       SetFP< D0,                       FPNeg< double, FPSub< double, FPMul< double, SD1, SD3, PPC64FPSCRRoundMode<S0> >, SD2, PPC64FPSCRRoundMode<S0> > > >}}},
00660     {"fnmsub.", MASK_X5F, OPCODE_X5F(63,  30, 1), 1, {{OpClassCode::fMUL,  { R0,CR1, -1}, {FPC, R1, R2, R3, -1, -1}, PPC64SetFPF< D0, D1, S0,               FPNeg< double, FPSub< double, FPMul< double, SD1, SD3, PPC64FPSCRRoundMode<S0> >, SD2, PPC64FPSCRRoundMode<S0> > > >}}},
00661     {"fnmsubs", MASK_X5F, OPCODE_X5F(59,  30, 0), 1, {{OpClassCode::fMUL,  { R0, -1, -1}, {FPC, R1, R2, R3, -1, -1},       SetFP< D0,         Cast< double, FPNeg<  float, FPSub<  float, FPMul<  float, SF1, SF3, PPC64FPSCRRoundMode<S0> >, SF2, PPC64FPSCRRoundMode<S0> > > > >}}},
00662     {"fnmsubs.",MASK_X5F, OPCODE_X5F(59,  30, 1), 1, {{OpClassCode::fMUL,  { R0,CR1, -1}, {FPC, R1, R2, R3, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< double, FPNeg<  float, FPSub<  float, FPMul<  float, SF1, SF3, PPC64FPSCRRoundMode<S0> >, SF2, PPC64FPSCRRoundMode<S0> > > > >}}},
00663 
00664 
00665     // conversion
00666 
00667     {"frsp",    MASK_X10F, OPCODE_X10F(63,  12, 0), 1, {{OpClassCode::fCONV,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         Cast< double, CastFP< float, SD1, PPC64FPSCRRoundMode<S0> > > >}}},
00668     {"frsp.",   MASK_X10F, OPCODE_X10F(63,  12, 1), 1, {{OpClassCode::fCONV,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< double, CastFP< float, SD1, PPC64FPSCRRoundMode<S0> > > >}}},
00669 
00670     {"fctid",   MASK_X10F, OPCODE_X10F(63, 814, 0), 1, {{OpClassCode::fCONV,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         PPC64FPToInt< s64, SD1, PPC64FPSCRRoundMode<S0> > >}}},
00671     {"fctid.",  MASK_X10F, OPCODE_X10F(63, 814, 1), 1, {{OpClassCode::fCONV,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, PPC64FPToInt< s64, SD1, PPC64FPSCRRoundMode<S0> > >}}},
00672 
00673     {"fctidz",  MASK_X10F, OPCODE_X10F(63, 815, 0), 1, {{OpClassCode::fCONV,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         PPC64FPToInt< s64, SD1, IntConst<int, FE_TOWARDZERO> > >}}},
00674     {"fctidz.", MASK_X10F, OPCODE_X10F(63, 815, 1), 1, {{OpClassCode::fCONV,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, PPC64FPToInt< s64, SD1, IntConst<int, FE_TOWARDZERO> > >}}},
00675 
00676     {"fctiw",   MASK_X10F, OPCODE_X10F(63,  14, 0), 1, {{OpClassCode::fCONV,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         Cast< s64, PPC64FPToInt< s32, SD1, PPC64FPSCRRoundMode<S0> > > >}}},
00677     {"fctiw.",  MASK_X10F, OPCODE_X10F(63,  14, 1), 1, {{OpClassCode::fCONV,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< s64, PPC64FPToInt< s32, SD1, PPC64FPSCRRoundMode<S0> > > >}}},
00678 
00679     {"fctiwz",  MASK_X10F, OPCODE_X10F(63,  15, 0), 1, {{OpClassCode::fCONV,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         Cast< s64, PPC64FPToInt< s32, SD1, IntConst<int, FE_TOWARDZERO> > > >}}},
00680     {"fctiwz.", MASK_X10F, OPCODE_X10F(63,  15, 1), 1, {{OpClassCode::fCONV,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< s64, PPC64FPToInt< s32, SD1, IntConst<int, FE_TOWARDZERO> > > >}}},
00681     
00682     {"fcfid",   MASK_X10F, OPCODE_X10F(63, 846, 0), 1, {{OpClassCode::fCONV,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         Cast< double, Cast< s64, S1 > > >}}},
00683     {"fcfid.",  MASK_X10F, OPCODE_X10F(63, 846, 1), 1, {{OpClassCode::fCONV,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, Cast< double, Cast< s64, S1 > > >}}},
00684 
00685     // double^gn
00686     {"frin",    MASK_X10F, OPCODE_X10F(63, 392, 0), 1, {{OpClassCode::fCONV,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         PPC64FRIN< SD1> >}}},
00687     {"frin.",   MASK_X10F, OPCODE_X10F(63, 392, 1), 1, {{OpClassCode::fCONV,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, PPC64FRIN< SD1> >}}},
00688 
00689     {"friz",    MASK_X10F, OPCODE_X10F(63, 424, 0), 1, {{OpClassCode::fCONV,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         PPC64FRIZ< SD1> >}}},
00690     {"friz.",   MASK_X10F, OPCODE_X10F(63, 424, 1), 1, {{OpClassCode::fCONV,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, PPC64FRIZ< SD1> >}}},
00691 
00692     {"frip",    MASK_X10F, OPCODE_X10F(63, 456, 0), 1, {{OpClassCode::fCONV,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         PPC64FRIP< SD1> >}}},
00693     {"frip.",   MASK_X10F, OPCODE_X10F(63, 456, 1), 1, {{OpClassCode::fCONV,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, PPC64FRIP< SD1> >}}},
00694 
00695     {"frim",    MASK_X10F, OPCODE_X10F(63, 488, 0), 1, {{OpClassCode::fCONV,  { R0, -1, -1}, {FPC, R1, -1, -1, -1, -1},       SetFP< D0,         PPC64FRIM< SD1> >}}},
00696     {"frim.",   MASK_X10F, OPCODE_X10F(63, 488, 1), 1, {{OpClassCode::fCONV,  { R0,CR1, -1}, {FPC, R1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, PPC64FRIM< SD1> >}}},
00697 
00698     // compare
00699     // <TODO> FPSCRtOZbg
00700     {"fcmpu",   MASK_X10, OPCODE_X10(63,   0), 1, {{OpClassCode::fADD,  { R0, -1, -1}, {FPC, R1, R2, -1, -1, -1}, Set< D0, PPC64FPCompare< double, SD1, SD2 > >}}},
00701     {"fcmpo",   MASK_X10, OPCODE_X10(63,  32), 1, {{OpClassCode::fADD,  { R0, -1, -1}, {FPC, R1, R2, -1, -1, -1}, Set< D0, PPC64FPCompare< double, SD1, SD2 > >}}},
00702 
00703     // fsel
00704 
00705     // control register
00706     {"mffs",    MASK_X10F, OPCODE_X10F(63, 583, 0), 1, {{OpClassCode::iMOV,  { R0, -1, -1}, {FPC, -1, -1, -1, -1, -1},         Set< D0,         S0 >}}},
00707     {"mffs.",   MASK_X10F, OPCODE_X10F(63, 583, 1), 1, {{OpClassCode::iMOV,  { R0,CR1, -1}, {FPC, -1, -1, -1, -1, -1}, PPC64SetFPF< D0, D1, S0, S0 >}}},
00708 
00709     //{"mcrfs",   MASK_X10, OPCODE_X10F(63,  64), 1, {{OpClassCode::iMOV,  {FPC, R0, -1}, {FPC, I0, -1, -1, -1, -1}, PPC64MCRFS< D0, D1, S0, S1 >}}},
00710 
00711     {"mtfsfi",  MASK_X10F, OPCODE_X10F(63, 134, 0), 1, {{OpClassCode::iMOV,  {FPC, -1, -1}, {FPC, I0, I1, -1, -1, -1},  PPC64SetFPSCR< D0,     PPC64MTFSFI< S0, S1, S2 > >}}},
00712     {"mtfsfi.", MASK_X10F, OPCODE_X10F(63, 134, 1), 1, {{OpClassCode::iMOV,  {FPC,CR1, -1}, {FPC, I0, I1, -1, -1, -1}, PPC64SetFPSCRF< D0, D1, PPC64MTFSFI< S0, S1, S2 > >}}},
00713     
00714     {"mtfsf",   MASK_X10F, OPCODE_X10F(63, 711, 0), 1, {{OpClassCode::iALU,  {FPC, -1, -1}, {FPC, I0, R0, -1, -1, -1},  PPC64SetFPSCR< D0,     PPC64MTFSF< S0, S1, S2 > >}}},
00715     {"mtfsf.",  MASK_X10F, OPCODE_X10F(63, 711, 1), 1, {{OpClassCode::iALU,  {FPC, -1, -1}, {FPC, I0, R0, -1, -1, -1}, PPC64SetFPSCRF< D0, D1, PPC64MTFSF< S0, S1, S2 > >}}},
00716 
00717     {"mtfsb0",  MASK_X10F, OPCODE_X10F(63,  70, 0), 1, {{OpClassCode::iALU,  {FPC, -1, -1}, {FPC, I0, -1, -1, -1, -1},  PPC64SetFPSCR< D0,     BitAnd< u64, S0, RotateR< u32, IntConst< u32, (u32)0x7fffffff >, S1 > > >}}},
00718     {"mtfsb0.", MASK_X10F, OPCODE_X10F(63,  70, 1), 1, {{OpClassCode::iALU,  {FPC,CR1, -1}, {FPC, I0, -1, -1, -1, -1}, PPC64SetFPSCRF< D0, D1, BitAnd< u64, S0, RotateR< u32, IntConst< u32, (u32)0x7fffffff >, S1 > > >}}},
00719     {"mtfsb1",  MASK_X10F, OPCODE_X10F(63,  38, 0), 1, {{OpClassCode::iALU,  {FPC, -1, -1}, {FPC, I0, -1, -1, -1, -1},  PPC64SetFPSCR< D0,     BitOr < u64, S0, RotateR< u32, IntConst< u32, (u32)0x80000000 >, S1 > > >}}},
00720     {"mtfsb1.", MASK_X10F, OPCODE_X10F(63,  38, 1), 1, {{OpClassCode::iALU,  {FPC,CR1, -1}, {FPC, I0, -1, -1, -1, -1}, PPC64SetFPSCRF< D0, D1, BitOr < u64, S0, RotateR< u32, IntConst< u32, (u32)0x80000000 >, S1 > > >}}},
00721 
00722 
00723     //
00724     // branch
00725     //
00726 
00727     // gcc 4.2.1RpCoCi
00728     // - gpH
00729     // - CALLbctrl gpH (LK=1bctrlH)
00730     // - blr, bctr  BH  0H
00731     {"b",       MASK_B, OPCODE_B(18, 0, 0), 1, {{OpClassCode::iBU,   { -1, -1, -1}, { I0, -1, -1, -1, -1, -1}, PPC64BranchRelUncond< S0 >}}},
00732     {"ba",      MASK_B, OPCODE_B(18, 1, 0), 1, {{OpClassCode::iBU,   { -1, -1, -1}, { I0, -1, -1, -1, -1, -1}, PPC64BranchAbsUncond< S0 >}}},
00733     {"bl",      MASK_B, OPCODE_B(18, 0, 1), 1, {{OpClassCode::CALL,  { LR, -1, -1}, { I0, -1, -1, -1, -1, -1}, PPC64CallRelUncond< D0, S0 >}}},
00734     {"bla",     MASK_B, OPCODE_B(18, 1, 1), 1, {{OpClassCode::CALL,  { LR, -1, -1}, { I0, -1, -1, -1, -1, -1}, PPC64CallAbsUncond< D0, S0 >}}},
00735 
00736     {"bf",      MASK_BC(034), OPCODE_BC(16, 0, 0, 004), 1, {{OpClassCode::iBC,  { -1, -1, -1}, { I1, R0, I0, -1, -1, -1}, PPC64BranchRelCond< S0, Compare< PPC64CRBit<S1, S2>, IntConst<u64, 0>, IntCondEqual<u64> > >}}},
00737     {"bt",      MASK_BC(034), OPCODE_BC(16, 0, 0, 014), 1, {{OpClassCode::iBC,  { -1, -1, -1}, { I1, R0, I0, -1, -1, -1}, PPC64BranchRelCond< S0, Compare< PPC64CRBit<S1, S2>, IntConst<u64, 0>, IntCondNotEqual<u64> > >}}},
00738     {"bdnzf",   MASK_BC(036), OPCODE_BC(16, 0, 0, 000), 1, {{OpClassCode::iBC,  {CTR, -1, -1}, { I1, R0, I0,CTR, -1, -1}, 
00739         PPC64BranchRelCond< S0, CondAnd< 
00740             Compare< PPC64DecCTR< D0, S3 >, IntConst<u64, 0>, IntCondNotEqual<u64> >,
00741             Compare< PPC64CRBit<S1, S2>, IntConst<u64, 0>, IntCondEqual<u64> >
00742         > >
00743     }}},
00744     {"bdzf",    MASK_BC(036), OPCODE_BC(16, 0, 0, 002), 1, {{OpClassCode::iBC,  {CTR, -1, -1}, { I1, R0, I0,CTR, -1, -1}, 
00745         PPC64BranchRelCond< S0, CondAnd< 
00746             Compare< PPC64DecCTR< D0, S3 >, IntConst<u64, 0>, IntCondEqual<u64> >,
00747             Compare< PPC64CRBit<S1, S2>, IntConst<u64, 0>, IntCondEqual<u64> >
00748         > >
00749     }}},
00750     {"bdnzt",   MASK_BC(036), OPCODE_BC(16, 0, 0, 010), 1, {{OpClassCode::iBC,  {CTR, -1, -1}, { I1, R0, I0,CTR, -1, -1}, 
00751         PPC64BranchRelCond< S0, CondAnd< 
00752             Compare< PPC64DecCTR< D0, S3 >, IntConst<u64, 0>, IntCondNotEqual<u64> >,
00753             Compare< PPC64CRBit<S1, S2>, IntConst<u64, 0>, IntCondNotEqual<u64> >
00754         > >
00755     }}},
00756     {"bdzt",    MASK_BC(036), OPCODE_BC(16, 0, 0, 012), 1, {{OpClassCode::iBC,  {CTR, -1, -1}, { I1, R0, I0,CTR, -1, -1}, 
00757         PPC64BranchRelCond< S0, CondAnd< 
00758             Compare< PPC64DecCTR< D0, S3 >, IntConst<u64, 0>, IntCondEqual<u64> >,
00759             Compare< PPC64CRBit<S1, S2>, IntConst<u64, 0>, IntCondNotEqual<u64> >
00760         > >
00761     }}},
00762     {"bdnz",    MASK_BC(026), OPCODE_BC(16, 0, 0, 020), 1, {{OpClassCode::iBC,  {CTR, -1, -1}, { I1,CTR, -1, -1, -1, -1}, PPC64BranchRelCond< S0, Compare< PPC64DecCTR< D0, S1 >, IntConst<u64, 0>, IntCondNotEqual<u64> > >}}},
00763     {"bdz",     MASK_BC(026), OPCODE_BC(16, 0, 0, 022), 1, {{OpClassCode::iBC,  {CTR, -1, -1}, { I1,CTR, -1, -1, -1, -1}, PPC64BranchRelCond< S0, Compare< PPC64DecCTR< D0, S1 >, IntConst<u64, 0>, IntCondEqual<u64> > >}}},
00764 
00765     {"bctr",    MASK_BCLR(024), OPCODE_BCLR(19,528, 0, 024, 0), 1, {{OpClassCode::iJUMP, { -1, -1, -1}, {CTR, -1, -1, -1, -1, -1}, PPC64BranchAbsUncond<  S0 >}}},
00766     {"bctrl",   MASK_BCLR(024), OPCODE_BCLR(19,528, 1, 024, 0), 1, {{OpClassCode::CALL_JUMP,  { LR, -1, -1}, {CTR, -1, -1, -1, -1, -1}, PPC64CallAbsUncond< D0, S0 >}}},
00767 
00768     {"blr",     MASK_BCLR(024), OPCODE_BCLR(19, 16, 0, 024, 0), 1, {{OpClassCode::RET,   { -1, -1, -1}, { LR, -1, -1, -1, -1, -1}, PPC64BranchAbsUncond< S0 >}}},
00769 
00770     {"bflr",    MASK_BCLR(034), OPCODE_BCLR(19, 16, 0, 004, 0), 1, {{OpClassCode::RETC,  { -1, -1, -1}, { LR, R0, I0, -1, -1, -1}, PPC64BranchAbsCond< S0, Compare< PPC64CRBit<S1, S2>, IntConst<u64, 0>, IntCondEqual<u64> > >}}},
00771     {"btlr",    MASK_BCLR(034), OPCODE_BCLR(19, 16, 0, 014, 0), 1, {{OpClassCode::RETC,  { -1, -1, -1}, { LR, R0, I0, -1, -1, -1}, PPC64BranchAbsCond< S0, Compare< PPC64CRBit<S1, S2>, IntConst<u64, 0>, IntCondNotEqual<u64> > >}}},
00772     {"bdnzflr", MASK_BCLR(036), OPCODE_BCLR(19, 16, 0, 000, 0), 1, {{OpClassCode::RETC,  {CTR, -1, -1}, { LR, R0, I0,CTR, -1, -1}, 
00773         PPC64BranchAbsCond< S0, CondAnd< 
00774             Compare< PPC64DecCTR< D0, S3 >, IntConst<u64, 0>, IntCondNotEqual<u64> >,
00775             Compare< PPC64CRBit<S1, S2>, IntConst<u64, 0>, IntCondEqual<u64> >
00776         > >
00777     }}},
00778     {"bdzflr",  MASK_BCLR(036), OPCODE_BCLR(19, 16, 0, 002, 0), 1, {{OpClassCode::RETC,  {CTR, -1, -1}, { LR, R0, I0,CTR, -1, -1}, 
00779         PPC64BranchAbsCond< S0, CondAnd< 
00780             Compare< PPC64DecCTR< D0, S3 >, IntConst<u64, 0>, IntCondEqual<u64> >,
00781             Compare< PPC64CRBit<S1, S2>, IntConst<u64, 0>, IntCondEqual<u64> >
00782         > >
00783     }}},
00784     {"bdnztlr", MASK_BCLR(036), OPCODE_BCLR(19, 16, 0, 010, 0), 1, {{OpClassCode::RETC,  {CTR, -1, -1}, { LR, R0, I0,CTR, -1, -1}, 
00785         PPC64BranchAbsCond< S0, CondAnd< 
00786             Compare< PPC64DecCTR< D0, S3 >, IntConst<u64, 0>, IntCondNotEqual<u64> >,
00787             Compare< PPC64CRBit<S1, S2>, IntConst<u64, 0>, IntCondNotEqual<u64> >
00788         > >
00789     }}},
00790     {"bdztlr",  MASK_BCLR(036), OPCODE_BCLR(19, 16, 0, 012, 0), 1, {{OpClassCode::RETC,  {CTR, -1, -1}, { LR, R0, I0,CTR, -1, -1}, 
00791         PPC64BranchAbsCond< S0, CondAnd< 
00792             Compare< PPC64DecCTR< D0, S3 >, IntConst<u64, 0>, IntCondEqual<u64> >,
00793             Compare< PPC64CRBit<S1, S2>, IntConst<u64, 0>, IntCondNotEqual<u64> >
00794         > >
00795     }}},
00796     {"bdnzlr",  MASK_BCLR(026), OPCODE_BCLR(19, 16, 0, 020, 0), 1, {{OpClassCode::RETC,  {CTR, -1, -1}, { LR,CTR, -1, -1, -1, -1}, PPC64BranchAbsCond< S0, Compare< PPC64DecCTR< D0, S1 >, IntConst<u64, 0>, IntCondNotEqual<u64> > >}}},
00797     {"bdzlr",   MASK_BCLR(026), OPCODE_BCLR(19, 16, 0, 022, 0), 1, {{OpClassCode::RETC,  {CTR, -1, -1}, { LR,CTR, -1, -1, -1, -1}, PPC64BranchAbsCond< S0, Compare< PPC64DecCTR< D0, S1 >, IntConst<u64, 0>, IntCondEqual<u64> > >}}},
00798 
00799     //
00800     // conditional register logical instructions
00801     //
00802     {"crand",   MASK_X10, OPCODE_X10(19, 257), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R0, I0, R1, I1, R2, I2}, PPC64SetCRBit< D0, S1, S0, PPC64CRAnd< S2, S3, S4, S5> >}}},
00803     {"crnand",  MASK_X10, OPCODE_X10(19, 225), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R0, I0, R1, I1, R2, I2}, PPC64SetCRBit< D0, S1, S0, PPC64CRNand< S2, S3, S4, S5> >}}},
00804     {"cror",    MASK_X10, OPCODE_X10(19, 449), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R0, I0, R1, I1, R2, I2}, PPC64SetCRBit< D0, S1, S0, PPC64CROr< S2, S3, S4, S5> >}}},
00805     {"crxor",   MASK_X10, OPCODE_X10(19, 193), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R0, I0, R1, I1, R2, I2}, PPC64SetCRBit< D0, S1, S0, PPC64CRXor< S2, S3, S4, S5> >}}},
00806     {"crnor",   MASK_X10, OPCODE_X10(19,  33), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R0, I0, R1, I1, R2, I2}, PPC64SetCRBit< D0, S1, S0, PPC64CRNor< S2, S3, S4, S5> >}}},
00807     {"creqv",   MASK_X10, OPCODE_X10(19, 289), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R0, I0, R1, I1, R2, I2}, PPC64SetCRBit< D0, S1, S0, PPC64CREqv< S2, S3, S4, S5> >}}},
00808     {"crandc",  MASK_X10, OPCODE_X10(19, 129), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R0, I0, R1, I1, R2, I2}, PPC64SetCRBit< D0, S1, S0, PPC64CRAndC< S2, S3, S4, S5> >}}},
00809     {"crorc",   MASK_X10, OPCODE_X10(19, 417), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R0, I0, R1, I1, R2, I2}, PPC64SetCRBit< D0, S1, S0, PPC64CROrC< S2, S3, S4, S5> >}}},
00810 
00811     {"mcrf",    MASK_X10, OPCODE_X10(19,   0), 1, {{OpClassCode::iALU,  { R0, -1, -1}, { R1, -1, -1, -1, -1, -1}, Set< D0, S0 >}}},
00812 
00813     // instruction synchronize : VOXbh
00814     {"isync",   MASK_X10, OPCODE_X10(19, 150), 1, {{OpClassCode::iNOP,  { -1, -1, -1}, { -1, -1, -1, -1, -1, -1}, NoOperation}}},
00815     
00816     //// タ
00817     //{"isync",   MASK_X10, OPCODE_X10(19, 150), 1, {{OpClassCode::syscall,  { -1, -1, -1}, { -1, -1, -1, -1, -1, -1}, NoOperation}}},
00818 
00819     // memory barrier : VOXbh
00820     {"sync",    MASK_X10, OPCODE_X10(31, 598), 1, {{OpClassCode::iNOP,  { -1, -1, -1}, { -1, -1, -1, -1, -1, -1}, NoOperation}}},
00821     {"eieio",   MASK_X10, OPCODE_X10(31, 854), 1, {{OpClassCode::iNOP,  { -1, -1, -1}, { -1, -1, -1, -1, -1, -1}, NoOperation}}},
00822 
00823     //
00824     // cache management
00825     //
00826 
00827     // cache management gpLbVubNTCY auxv, AT_DCACHEBSIZE 
00828     // cf.) glibc/sysdeps/unix/sysv/linux/powerpc/libc-start.c
00829     // i0jCglibcdcbzgpBmemsetdcbzgp
00830 
00831     // 
00832     // data cache block touch
00833     {"dcbt",    MASK_X10, OPCODE_X10(31, 278), 1, {{OpClassCode::iNOP,  { -1, -1, -1}, { -1, -1, -1, -1, -1, -1}, NoOperation}}},
00834     // data cache block touch for store
00835     {"dcbtst",  MASK_X10, OPCODE_X10(31, 246), 1, {{OpClassCode::iNOP,  { -1, -1, -1}, { -1, -1, -1, -1, -1, -1}, NoOperation}}},
00836 
00837     // data cache block set to zero : タ0XgA
00838     //{"dcbz",    MASK_X10, OPCODE_X10(31,1014), 1, {{OpClassCode::iST,  { -1, -1, -1}, { -1, -1, -1, -1, -1, -1}, }}},
00839 };
00840 
00841 //
00842 // split load Store
00843 //
00844 PPC64Converter::OpDef PPC64Converter::m_OpDefsSplitLoadStore[] =
00845 {
00846     {}
00847 };
00848 
00849 //
00850 // non-split load Store
00851 //
00852 PPC64Converter::OpDef PPC64Converter::m_OpDefsNonSplitLoadStore[] =
00853 {
00854     // <FIXME> RA=0? g
00855     // integer load
00856     {"lbz",   MASK_OP, OPCODE_OP(34), 1, {
00857         {OpClassCode::iLD,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0,                Load< u8,     IntAdd< u64, S0, S1 > > >}
00858     }},
00859     {"lbzu",  MASK_OP, OPCODE_OP(35), 1, {
00860         {OpClassCode::iLD,  { R0, R1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0, PPC64LoadWithUpdate< u8, D1, IntAdd< u64, S0, S1 > > >}
00861     }},
00862     {"lbzx",  MASK_X10, OPCODE_X10(31,  87), 1, {
00863         {OpClassCode::iLD,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0,                Load< u8,     IntAdd< u64, S0, S1 > > >}
00864     }},
00865     {"lbzx",  MASK_X10|MASK_RA, OPCODE_X10(31,  87), 1, {   // RA=0
00866         {OpClassCode::iLD,  { R0, -1, -1}, { R2, -1, -1, -1, -1, -1}, Set< D0,                Load< u8,     S0 > >}
00867     }},
00868     {"lbzux", MASK_X10, OPCODE_X10(31, 119), 1, {
00869         {OpClassCode::iLD,  { R0, R1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0, PPC64LoadWithUpdate< u8, D1, IntAdd< u64, S0, S1 > > >}
00870     }},
00871 
00872     {"lhz",   MASK_OP, OPCODE_OP(40), 1, {
00873         {OpClassCode::iLD,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0,                Load< u16,     IntAdd< u64, S0, S1 > > >}
00874     }},
00875     {"lhzu",  MASK_OP, OPCODE_OP(41), 1, {
00876         {OpClassCode::iLD,  { R0, R1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0, PPC64LoadWithUpdate< u16, D1, IntAdd< u64, S0, S1 > > >}
00877     }},
00878     {"lhzx",  MASK_X10, OPCODE_X10(31, 279), 1, {
00879         {OpClassCode::iLD,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0,                Load< u16,     IntAdd< u64, S0, S1 > > >}
00880     }},
00881     {"lhzx",  MASK_X10|MASK_RA, OPCODE_X10(31, 279), 1, {   // RA=0
00882         {OpClassCode::iLD,  { R0, -1, -1}, { R2, -1, -1, -1, -1, -1}, Set< D0,                Load< u16,     S0 > >}
00883     }},
00884     {"lhzux", MASK_X10, OPCODE_X10(31, 311), 1, {
00885         {OpClassCode::iLD,  { R0, R1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0, PPC64LoadWithUpdate< u16, D1, IntAdd< u64, S0, S1 > > >}
00886     }},
00887 
00888     {"lha",   MASK_OP, OPCODE_OP(42), 1, {
00889         {OpClassCode::iLD,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, SetSext< D0,                Load< u16,     IntAdd< u64, S0, S1 > > >}
00890     }},
00891     {"lhau",  MASK_OP, OPCODE_OP(43), 1, {
00892         {OpClassCode::iLD,  { R0, R1, -1}, { R1, I0, -1, -1, -1, -1}, SetSext< D0, PPC64LoadWithUpdate< u16, D1, IntAdd< u64, S0, S1 > > >}
00893     }},
00894     {"lhax",  MASK_X10, OPCODE_X10(31, 343), 1, {
00895         {OpClassCode::iLD,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, SetSext< D0,                Load< u16,     IntAdd< u64, S0, S1 > > >}
00896     }},
00897     {"lhax",  MASK_X10|MASK_RA, OPCODE_X10(31, 343), 1, {   // RA=0
00898         {OpClassCode::iLD,  { R0, -1, -1}, { R2, -1, -1, -1, -1, -1}, SetSext< D0,                Load< u16,     S0 > >}
00899     }},
00900     {"lhaux", MASK_X10, OPCODE_X10(31, 375), 1, {
00901         {OpClassCode::iLD,  { R0, R1, -1}, { R1, R2, -1, -1, -1, -1}, SetSext< D0, PPC64LoadWithUpdate< u16, D1, IntAdd< u64, S0, S1 > > >}
00902     }},
00903 
00904     {"lwz",   MASK_OP, OPCODE_OP(32), 1, {
00905         {OpClassCode::iLD,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0,                Load< u32,     IntAdd< u64, S0, S1 > > >}
00906     }},
00907     {"lwzu",  MASK_OP, OPCODE_OP(33), 1, {
00908         {OpClassCode::iLD,  { R0, R1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0, PPC64LoadWithUpdate< u32, D1, IntAdd< u64, S0, S1 > > >}
00909     }},
00910     {"lwzx",  MASK_X10, OPCODE_X10(31,  23), 1, {
00911         {OpClassCode::iLD,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0,                Load< u32,     IntAdd< u64, S0, S1 > > >}
00912     }},
00913     {"lwzx",  MASK_X10|MASK_RA, OPCODE_X10(31,  23), 1, {   // RA=0
00914         {OpClassCode::iLD,  { R0, -1, -1}, { R2, -1, -1, -1, -1, -1}, Set< D0,                Load< u32,     S0 > >}
00915     }},
00916     {"lwzux", MASK_X10, OPCODE_X10(31,  55), 1, {
00917         {OpClassCode::iLD,  { R0, R1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0, PPC64LoadWithUpdate< u32, D1, IntAdd< u64, S0, S1 > > >}
00918     }},
00919 
00920     {"lwa",   MASK_X2, OPCODE_X2(58, 2), 1, {
00921         {OpClassCode::iLD,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, SetSext< D0,                Load< u32,     IntAdd< u64, S0, LShiftL< s64, S1, IntConst<unsigned int, 2>, 63 > > > >}
00922     }},
00923     {"lwax",  MASK_X10, OPCODE_X10(31, 341), 1, {
00924         {OpClassCode::iLD,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, SetSext< D0,                Load< u32,     IntAdd< u64, S0, S1 > > >}
00925     }},
00926     {"lwax",  MASK_X10|MASK_RA, OPCODE_X10(31, 341), 1, {   // RA=0
00927         {OpClassCode::iLD,  { R0, -1, -1}, { R2, -1, -1, -1, -1, -1}, SetSext< D0,                Load< u32,     S0 > >}
00928     }},
00929     {"lwaux", MASK_X10, OPCODE_X10(31, 373), 1, {
00930         {OpClassCode::iLD,  { R0, R1, -1}, { R1, R2, -1, -1, -1, -1}, SetSext< D0, PPC64LoadWithUpdate< u32, D1, IntAdd< u64, S0, S1 > > >}
00931     }},
00932 
00933     {"ld",    MASK_X2, OPCODE_X2(58, 0), 1, {
00934         {OpClassCode::iLD,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0,                Load< u64,     IntAdd< u64, S0, LShiftL< s64, S1, IntConst<unsigned int, 2>, 63 > > > >}
00935     }},
00936     {"ldu",   MASK_X2, OPCODE_X2(58, 1), 1, {
00937         {OpClassCode::iLD,  { R0, R1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0, PPC64LoadWithUpdate< u64, D1, IntAdd< u64, S0, LShiftL< s64, S1, IntConst<unsigned int, 2>, 63 > > > >}
00938     }},
00939     {"ldx",   MASK_X10, OPCODE_X10(31,  21), 1, {
00940         {OpClassCode::iLD,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0,                Load< u64,     IntAdd< u64, S0, S1 > > >}
00941     }},
00942     {"ldx",   MASK_X10|MASK_RA, OPCODE_X10(31,  21), 1, {   // RA=0
00943         {OpClassCode::iLD,  { R0, -1, -1}, { R2, -1, -1, -1, -1, -1}, Set< D0,                Load< u64,     S0 > >}
00944     }},
00945     {"ldux",  MASK_X10, OPCODE_X10(31,  53), 1, {
00946         {OpClassCode::iLD,  { R0, R1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0, PPC64LoadWithUpdate< u64, D1, IntAdd< u64, S0, S1 > > >}
00947     }},
00948 
00949     // integer store
00950     {"stb",   MASK_OP, OPCODE_OP(38), 1, {
00951         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, I0, -1, -1, -1},                Store< u8,     S0, IntAdd< u64, S1, S2 > >}
00952     }},
00953     {"stbu",  MASK_OP, OPCODE_OP(39), 1, {
00954         {OpClassCode::iST,  { R1, -1, -1}, { R0, R1, I0, -1, -1, -1}, PPC64StoreWithUpdate< u8, D0, S0, IntAdd< u64, S1, S2 > >}
00955     }},
00956     {"stbx",  MASK_X10, OPCODE_X10(31, 215), 1, {
00957         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, R2, -1, -1, -1},                Store< u8,     S0, IntAdd< u64, S1, S2 > >}
00958     }},
00959     {"stbx",  MASK_X10|MASK_RA, OPCODE_X10(31, 215), 1, {   // RA=0
00960         {OpClassCode::iST,  { -1, -1, -1}, { R0, R2, -1, -1, -1, -1},                Store< u8,     S0, S1 >}
00961     }},
00962     {"stbux", MASK_X10, OPCODE_X10(31, 247), 1, {
00963         {OpClassCode::iST,  { R1, -1, -1}, { R0, R1, R2, -1, -1, -1}, PPC64StoreWithUpdate< u8, D0, S0, IntAdd< u64, S1, S2 > >}
00964     }},
00965 
00966     {"sth",   MASK_OP, OPCODE_OP(44), 1, {
00967         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, I0, -1, -1, -1},                Store< u16,     S0, IntAdd< u64, S1, S2 > >}
00968     }},
00969     {"sthu",  MASK_OP, OPCODE_OP(45), 1, {
00970         {OpClassCode::iST,  { R1, -1, -1}, { R0, R1, I0, -1, -1, -1}, PPC64StoreWithUpdate< u16, D0, S0, IntAdd< u64, S1, S2 > >}
00971     }},
00972     {"sthx",  MASK_X10, OPCODE_X10(31, 407), 1, {
00973         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, R2, -1, -1, -1},                Store< u16,     S0, IntAdd< u64, S1, S2 > >}
00974     }},
00975     {"sthx",  MASK_X10|MASK_RA, OPCODE_X10(31, 407), 1, {   // RA=0
00976         {OpClassCode::iST,  { -1, -1, -1}, { R0, R2, -1, -1, -1, -1},                Store< u16,     S0, S1 >}
00977     }},
00978     {"sthux", MASK_X10, OPCODE_X10(31, 439), 1, {
00979         {OpClassCode::iST,  { R1, -1, -1}, { R0, R1, R2, -1, -1, -1}, PPC64StoreWithUpdate< u16, D0, S0, IntAdd< u64, S1, S2 > >}
00980     }},
00981 
00982     {"stw",   MASK_OP, OPCODE_OP(36), 1, {
00983         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, I0, -1, -1, -1},                Store< u32,     S0, IntAdd< u64, S1, S2 > >}
00984     }},
00985     {"stwu",  MASK_OP, OPCODE_OP(37), 1, {
00986         {OpClassCode::iST,  { R1, -1, -1}, { R0, R1, I0, -1, -1, -1}, PPC64StoreWithUpdate< u32, D0, S0, IntAdd< u64, S1, S2 > >}
00987     }},
00988     {"stwx",  MASK_X10, OPCODE_X10(31, 151), 1, {
00989         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, R2, -1, -1, -1},                Store< u32,     S0, IntAdd< u64, S1, S2 > >}
00990     }},
00991     {"stwx",  MASK_X10|MASK_RA, OPCODE_X10(31, 151), 1, {   // RA=0
00992         {OpClassCode::iST,  { -1, -1, -1}, { R0, R2, -1, -1, -1, -1},                Store< u32,     S0, S1 >}
00993     }},
00994     {"stwux", MASK_X10, OPCODE_X10(31, 183), 1, {
00995         {OpClassCode::iST,  { R1, -1, -1}, { R0, R1, R2, -1, -1, -1}, PPC64StoreWithUpdate< u32, D0, S0, IntAdd< u64, S1, S2 > >}
00996     }},
00997 
00998     {"std",   MASK_X2, OPCODE_X2(62, 0), 1, {
00999         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, I0, -1, -1, -1},                Store< u64,     S0, IntAdd< u64, S1, LShiftL< s64, S2, IntConst<unsigned int, 2>, 63 > > >}
01000     }},
01001     {"stdu",  MASK_X2, OPCODE_X2(62, 1), 1, {
01002         {OpClassCode::iST,  { R1, -1, -1}, { R0, R1, I0, -1, -1, -1}, PPC64StoreWithUpdate< u64, D0, S0, IntAdd< u64, S1, LShiftL< s64, S2, IntConst<unsigned int, 2>, 63 > > >}
01003     }},
01004     {"stdx",  MASK_X10, OPCODE_X10(31, 149), 1, {
01005         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, R2, -1, -1, -1},                Store< u64,     S0, IntAdd< u64, S1, S2 > >}
01006     }},
01007     {"stdx",  MASK_X10|MASK_RA, OPCODE_X10(31, 149), 1, {   // RA=0
01008         {OpClassCode::iST,  { -1, -1, -1}, { R0, R2, -1, -1, -1, -1},                Store< u64,     S0, S1 >}
01009     }},
01010     {"stdux", MASK_X10, OPCODE_X10(31, 181), 1, {
01011         {OpClassCode::iST,  { R1, -1, -1}, { R0, R1, R2, -1, -1, -1}, PPC64StoreWithUpdate< u64, D0, S0, IntAdd< u64, S1, S2 > >}
01012     }},
01013 
01014     // FP load
01015     {"lfs",   MASK_OP, OPCODE_OP(48), 1, {
01016         {OpClassCode::iLD,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, SetFP< D0, Cast<double, AsFP< float,                Load< u32,     IntAdd< u64, S0, S1 > > > > >}
01017     }},
01018     {"lfsu",  MASK_OP, OPCODE_OP(49), 1, {
01019         {OpClassCode::iLD,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, SetFP< D0, Cast<double, AsFP< float, PPC64LoadWithUpdate< u32, D1, IntAdd< u64, S0, S1 > > > > >}
01020     }},
01021     {"lfsx",  MASK_X10, OPCODE_X10(31, 535), 1, {
01022         {OpClassCode::iLD,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, SetFP< D0, Cast<double, AsFP< float,                Load< u32,     IntAdd< u64, S0, S1 > > > > >}
01023     }},
01024     {"lfsx",  MASK_X10|MASK_RA, OPCODE_X10(31, 535), 1, {   // RA=0
01025         {OpClassCode::iLD,  { R0, -1, -1}, { R2, -1, -1, -1, -1, -1}, SetFP< D0, Cast<double, AsFP< float,                Load< u32,     S0 > > > >}
01026     }},
01027     {"lfsux", MASK_X10, OPCODE_X10(31, 567), 1, {
01028         {OpClassCode::iLD,  { R0, R1, -1}, { R1, R2, -1, -1, -1, -1}, SetFP< D0, Cast<double, AsFP< float, PPC64LoadWithUpdate< u32, D1, IntAdd< u64, S0, S1 > > > > >}
01029     }},
01030 
01031     {"lfd",   MASK_OP, OPCODE_OP(50), 1, {
01032         {OpClassCode::iLD,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0,                Load< u64,     IntAdd< u64, S0, S1 > > >}
01033     }},
01034     {"lfdu",  MASK_OP, OPCODE_OP(51), 1, {
01035         {OpClassCode::iLD,  { R0, -1, -1}, { R1, I0, -1, -1, -1, -1}, Set< D0, PPC64LoadWithUpdate< u64, D1, IntAdd< u64, S0, S1 > > >}
01036     }},
01037     {"lfdx",  MASK_X10, OPCODE_X10(31, 599), 1, {
01038         {OpClassCode::iLD,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0,                Load< u64,     IntAdd< u64, S0, S1 > > >}
01039     }},
01040     {"lfdx",  MASK_X10|MASK_RA, OPCODE_X10(31, 599), 1, {   // RA=0
01041         {OpClassCode::iLD,  { R0, -1, -1}, { R2, -1, -1, -1, -1, -1}, Set< D0,                Load< u64,     S0 > >}
01042     }},
01043     {"lfdux", MASK_X10, OPCODE_X10(31, 631), 1, {
01044         {OpClassCode::iLD,  { R0, R1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0, PPC64LoadWithUpdate< u64, D1, IntAdd< u64, S0, S1 > > >}
01045     }},
01046 
01047     // FP store
01048     {"stfs",  MASK_OP, OPCODE_OP(52), 1, {
01049         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, I0, -1, -1, -1},                Store< u32,     AsInt< u32, SF0>, IntAdd< u64, S1, S2 > >}
01050     }},
01051     {"stfsu", MASK_OP, OPCODE_OP(53), 1, {
01052         {OpClassCode::iST,  { R1, -1, -1}, { R0, R1, I0, -1, -1, -1}, PPC64StoreWithUpdate< u32, D0, AsInt< u32, SF0>, IntAdd< u64, S1, S2 > >}
01053     }},
01054     {"stfsx", MASK_X10, OPCODE_X10(31, 663), 1, {
01055         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, R2, -1, -1, -1},                Store< u32,     AsInt< u32, SF0>, IntAdd< u64, S1, S2 > >}
01056     }},
01057     {"stfsx", MASK_X10|MASK_RA, OPCODE_X10(31, 663), 1, {   // RA=0
01058         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, R2, -1, -1, -1},                Store< u32,     AsInt< u32, SF0>, S1 >}
01059     }},
01060     {"stfsux",MASK_X10, OPCODE_X10(31, 695), 1, {
01061         {OpClassCode::iST,  { R1, -1, -1}, { R0, R1, R2, -1, -1, -1}, PPC64StoreWithUpdate< u32, D0, AsInt< u32, SF0>, IntAdd< u64, S1, S2 > >}
01062     }},
01063 
01064     {"stfd",  MASK_OP, OPCODE_OP(54), 1, {
01065         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, I0, -1, -1, -1},                Store< u64,     S0, IntAdd< u64, S1, S2 > >}
01066     }},
01067     {"stfdu", MASK_OP, OPCODE_OP(55), 1, {
01068         {OpClassCode::iST,  { R1, -1, -1}, { R0, R1, I0, -1, -1, -1}, PPC64StoreWithUpdate< u64, D0, S0, IntAdd< u64, S1, S2 > >}
01069     }},
01070     {"stfdx", MASK_X10, OPCODE_X10(31, 727), 1, {
01071         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, R2, -1, -1, -1},                Store< u64,     S0, IntAdd< u64, S1, S2 > >}
01072     }},
01073     {"stfdx", MASK_X10|MASK_RA, OPCODE_X10(31, 727), 1, {   // RA=0
01074         {OpClassCode::iST,  { -1, -1, -1}, { R0, R2, -1, -1, -1, -1},                Store< u64,     S0, S1 >}
01075     }},
01076     {"stfdux",MASK_X10, OPCODE_X10(31, 759), 1, {
01077         {OpClassCode::iST,  { R1, -1, -1}, { R0, R1, R2, -1, -1, -1}, PPC64StoreWithUpdate< u64, D0, S0, IntAdd< u64, S1, S2 > >}
01078     }},
01079 
01080     {"stfiwx", MASK_X10, OPCODE_X10(31, 983), 1, {
01081         {OpClassCode::iST,  { -1, -1, -1}, { R0, R1, R2, -1, -1, -1},                Store< u32,     S0, IntAdd< u64, S1, S2 > >}
01082     }},
01083     {"stfiwx", MASK_X10|MASK_RA, OPCODE_X10(31, 983), 1, {  // RA=0
01084         {OpClassCode::iST,  { -1, -1, -1}, { R0, R2, -1, -1, -1, -1},                Store< u32,     S0, S1 >}
01085     }},
01086 
01087     // lwarx, stwcxK
01088     {"lwarx",  MASK_X10, OPCODE_X10(31,  20), 1, {
01089         {OpClassCode::iLD,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0,                Load< u32,     IntAdd< u64, S0, S1 > > >}
01090     }},
01091     {"lwarx",  MASK_X10|MASK_RA, OPCODE_X10(31,  20), 1, {  // RA=0
01092         {OpClassCode::iLD,  { R0, -1, -1}, { R2, -1, -1, -1, -1, -1}, Set< D0,                Load< u32,     S0 > >}
01093     }},
01094     {"stwcx",  MASK_X10, OPCODE_X10(31, 150), 1, {
01095         {OpClassCode::iST,  {CR0, -1, -1}, { R0, R1, R2, -1, -1, -1},
01096             Sequence2<
01097                 Store< u32, S0, IntAdd< u64, S1, S2 > >,
01098                 Set< D0, IntConst<u64, 0x2> >
01099             >
01100         }
01101     }},
01102     {"stwcx.",  MASK_X10|MASK_RA, OPCODE_X10(31, 150), 1, { // RA=0
01103         {OpClassCode::iST,  {CR0, -1, -1}, { R0, R2, -1, -1, -1, -1},
01104             Sequence2<
01105                 Store< u32, S0, S1 >,
01106                 Set< D0, IntConst<u64, 0x2> >
01107             >
01108         }
01109     }},
01110 
01111     {"ldarx",  MASK_X10, OPCODE_X10(31,  84), 1, {
01112         {OpClassCode::iLD,  { R0, -1, -1}, { R1, R2, -1, -1, -1, -1}, Set< D0,                Load< u64,     IntAdd< u64, S0, S1 > > >}
01113     }},
01114     {"ldarx",  MASK_X10|MASK_RA, OPCODE_X10(31,  84), 1, {  // RA=0
01115         {OpClassCode::iLD,  { R0, -1, -1}, { R2, -1, -1, -1, -1, -1}, Set< D0,                Load< u64,     S0 > >}
01116     }},
01117     {"stdcx.",  MASK_X10, OPCODE_X10(31, 214), 1, {
01118         {OpClassCode::iST,  {CR0, -1, -1}, { R0, R1, R2, -1, -1, -1},
01119             Sequence2<
01120                 Store< u64, S0, IntAdd< u64, S1, S2 > >,
01121                 Set< D0, IntConst<u64, 0x2> >
01122             >
01123         }
01124     }},
01125     {"stdcx",  MASK_X10|MASK_RA, OPCODE_X10(31, 214), 1, {  // RA=0
01126         {OpClassCode::iST,  {CR0, -1, -1}, { R0, R2, -1, -1, -1, -1},
01127             Sequence2<
01128                 Store< u64, S0, S1 >,
01129                 Set< D0, IntConst<u64, 0x2> >
01130             >
01131         }
01132     }},};
01133 
01134 
01135 //
01136 // PPC64Converter
01137 //
01138 
01139 
01140 PPC64Converter::PPC64Converter()
01141 {
01142     AddToOpMap(m_OpDefsBase, sizeof(m_OpDefsBase)/sizeof(OpDef));
01143     if (IsSplitLoadStoreEnabled()) {
01144         // <TODO> split load/store
01145         cerr << "warning: split load/store not yet implemented" << endl;
01146         AddToOpMap(m_OpDefsNonSplitLoadStore, sizeof(m_OpDefsNonSplitLoadStore)/sizeof(OpDef));
01147         //AddToOpMap(m_OpDefsSplitLoadStore, sizeof(m_OpDefsSplitLoadStore)/sizeof(OpDef));
01148     }
01149     else{
01150         AddToOpMap(m_OpDefsNonSplitLoadStore, sizeof(m_OpDefsNonSplitLoadStore)/sizeof(OpDef));
01151     }
01152 }
01153 
01154 PPC64Converter::~PPC64Converter()
01155 {
01156 }
01157 
01158 // srcTemplate IyhCWX^Clindex
01159 std::pair<PPC64Converter::OperandType, int> PPC64Converter::GetActualSrcOperand(int srcTemplate, const DecodedInsn& decoded) const
01160 {
01161     typedef std::pair<OperandType, int> RetType;
01162     if (srcTemplate == -1) {
01163         return RetType(OpInfoType::NONE, 0);
01164     }
01165     else if (ImmTemplateBegin <= srcTemplate && srcTemplate <= ImmTemplateEnd) {
01166         return RetType(OpInfoType::IMM, srcTemplate - ImmTemplateBegin);
01167     }
01168     else  {
01169         return RetType(OpInfoType::REG, GetActualRegNumber(srcTemplate, decoded) );
01170     }
01171 }
01172 
01173 // regTemplate タWX^
01174 int PPC64Converter::GetActualRegNumber(int regTemplate, const DecodedInsn& decoded) const
01175 {
01176     if (regTemplate == -1) {
01177         return -1;
01178     }
01179     else if (RegTemplateBegin <= regTemplate && regTemplate <= RegTemplateEnd) {
01180         return decoded.Reg[regTemplate - RegTemplateBegin];
01181     }
01182     else if (0 <= regTemplate && regTemplate < PPC64Info::RegisterCount) {
01183         return regTemplate;
01184     }
01185     else {
01186         ASSERT(0, "PPC64Converter Logic Error : invalid regTemplate");
01187         return -1;
01188     }
01189 }
01190 
01191 // WX^regNum[WX^
01192 bool PPC64Converter::IsZeroReg(int regNum) const
01193 {
01194     // PowerPC [WX^
01195     return false;
01196 }
01197 
01198 
01199 void PPC64Converter::PPC64UnknownOperation(OpEmulationState* opState)
01200 {
01201     u32 codeWord = static_cast<u32>( SrcOperand<0>()(opState) );
01202 
01203     DecoderType decoder;
01204     DecodedInsn decoded;
01205     decoder.Decode( codeWord, &decoded);
01206 
01207     stringstream ss;
01208     u32 opcode = (codeWord >> 26) & 0x3f;
01209     ss << "unknown instruction : " << hex << setw(8) << codeWord << endl;
01210     ss << "\topcode : " << hex << opcode << endl;
01211     ss << "\tregs : " << hex;
01212     copy(decoded.Reg.begin(), decoded.Reg.end(), ostream_iterator<int>(ss, ", "));
01213     ss << endl;
01214     ss << "\timms : " << hex;
01215     copy(decoded.Imm.begin(), decoded.Imm.end(), ostream_iterator<u64>(ss, ", "));
01216     ss << endl;
01217 
01218     THROW_RUNTIME_ERROR(ss.str().c_str());
01219 }
01220 
01221 const PPC64Converter::OpDef* PPC64Converter::GetOpDefUnknown() const
01222 {
01223     return &m_OpDefUnknown;
01224 }

Onikiri2に対してTue Jun 18 14:34:19 2013に生成されました。  doxygen 1.4.7