00001 // 00002 // Copyright (c) 2005-2008 Kenichi Watanabe. 00003 // Copyright (c) 2005-2008 Yasuhiro Watari. 00004 // Copyright (c) 2005-2008 Hironori Ichibayashi. 00005 // Copyright (c) 2008-2009 Kazuo Horio. 00006 // Copyright (c) 2009-2013 Naruki Kurata. 00007 // Copyright (c) 2005-2013 Ryota Shioya. 00008 // Copyright (c) 2005-2013 Masahiro Goshima. 00009 // 00010 // This software is provided 'as-is', without any express or implied 00011 // warranty. In no event will the authors be held liable for any damages 00012 // arising from the use of this software. 00013 // 00014 // Permission is granted to anyone to use this software for any purpose, 00015 // including commercial applications, and to alter it and redistribute it 00016 // freely, subject to the following restrictions: 00017 // 00018 // 1. The origin of this software must not be misrepresented; you must not 00019 // claim that you wrote the original software. If you use this software 00020 // in a product, an acknowledgment in the product documentation would be 00021 // appreciated but is not required. 00022 // 00023 // 2. Altered source versions must be plainly marked as such, and must not be 00024 // misrepresented as being the original software. 00025 // 00026 // 3. This notice may not be removed or altered from any source 00027 // distribution. 00028 // 00029 // 00030 00031 00032 #include <pch.h> 00033 00034 #include "Sim/Memory/Cache/MemoryAccessEndEvent.h" 00035 00036 00037 using namespace Onikiri; 00038 00039 CacheAccessEndEvent::CacheAccessEndEvent( 00040 const CacheAccess& access, 00041 AccessQueueIterator target, 00042 CacheAccessRequestQueue* accessReqQueue 00043 ) : 00044 m_access ( access ), 00045 m_target ( target ), 00046 m_accessReqQueue( accessReqQueue ) 00047 { 00048 } 00049 00050 // m_addrPendingAccessIPendingAccessO 00051 void CacheAccessEndEvent::Update() 00052 { 00053 m_accessReqQueue->Pop( m_access, m_target ); 00054 } 00055 00056 00057 00058 MissedAccessRearchEvent::MissedAccessRearchEvent( 00059 const CacheAccess& access, 00060 CacheMissedAccessList::AccessListIterator target, 00061 CacheMissedAccessList* accessList 00062 ) : 00063 m_access ( access ), 00064 m_target ( target ), 00065 m_pendingAccess ( accessList ) 00066 { 00067 } 00068 00069 // m_addrPendingAccessIPendingAccessO 00070 void MissedAccessRearchEvent::Update() 00071 { 00072 m_pendingAccess->Remove( m_access, m_target ); 00073 }