src/Sim/Predictor/LatPred/LatPred.cpp

説明を見る。
00001 // 
00002 // Copyright (c) 2005-2008 Kenichi Watanabe.
00003 // Copyright (c) 2005-2008 Yasuhiro Watari.
00004 // Copyright (c) 2005-2008 Hironori Ichibayashi.
00005 // Copyright (c) 2008-2009 Kazuo Horio.
00006 // Copyright (c) 2009-2013 Naruki Kurata.
00007 // Copyright (c) 2005-2013 Ryota Shioya.
00008 // Copyright (c) 2005-2013 Masahiro Goshima.
00009 // 
00010 // This software is provided 'as-is', without any express or implied
00011 // warranty. In no event will the authors be held liable for any damages
00012 // arising from the use of this software.
00013 // 
00014 // Permission is granted to anyone to use this software for any purpose,
00015 // including commercial applications, and to alter it and redistribute it
00016 // freely, subject to the following restrictions:
00017 // 
00018 // 1. The origin of this software must not be misrepresented; you must not
00019 // claim that you wrote the original software. If you use this software
00020 // in a product, an acknowledgment in the product documentation would be
00021 // appreciated but is not required.
00022 // 
00023 // 2. Altered source versions must be plainly marked as such, and must not be
00024 // misrepresented as being the original software.
00025 // 
00026 // 3. This notice may not be removed or altered from any source
00027 // distribution.
00028 // 
00029 // 
00030 
00031 
00032 #include <pch.h>
00033 
00034 #include "Sim/Predictor/LatPred/LatPred.h"
00035 #include "Sim/Predictor/HitMissPred/CounterBasedHitMissPred.h"
00036 #include "Sim/Predictor/HitMissPred/StaticHitMissPred.h"
00037 #include "Sim/ExecUnit/ExecUnitIF.h"
00038 #include "Sim/Pipeline/Scheduler/Scheduler.h"
00039 #include "Sim/Op/Op.h"
00040 #include "Sim/Core/Core.h"
00041 
00042 using namespace Onikiri;
00043 
00044 namespace Onikiri
00045 {
00046     HookPoint<LatPred> LatPred::s_latencyPredictionHook;
00047 }; // Onikiri
00048 
00049 LatPred::LatPred() :
00050     m_execLatencyInfo(0),
00051     m_hmPredictor(0),
00052     m_core(0),
00053     m_numHit(0),
00054     m_numMiss(0),
00055     m_numLoadHitPredToHit(0),
00056     m_numLoadHitPredToMiss(0),
00057     m_numLoadMissPredToHit(0),
00058     m_numLoadMissPredToMiss(0)
00059 {
00060 }
00061 
00062 LatPred::~LatPred()
00063 {
00064     ReleaseParam();
00065 }
00066 
00067 void LatPred::Initialize(InitPhase phase)
00068 {
00069     if(phase == INIT_PRE_CONNECTION){
00070         LoadParam();
00071     }
00072     else if(phase == INIT_POST_CONNECTION){
00073         CheckNodeInitialized( "execLatencyInfo", m_execLatencyInfo );
00074         CheckNodeInitialized( "hmPredictor", m_hmPredictor );
00075     }
00076 }
00077 
00078 // CeV\
00079 // 2xiL1/L2j\
00080 // L1~XCL2qbg\
00081 void LatPred::Predict(OpIterator op)
00082 {
00083     const OpClass& opClass = op->GetOpClass();
00084 
00085     LatPredResult result;
00086 
00087     s_latencyPredictionHook.Trigger(op, this, HookType::HOOK_BEFORE);
00088 
00089     if( !s_latencyPredictionHook.HasAround() ) {
00090         // {
00091         // Load/store hit miss prediction
00092         // CeV\XPW[Oft@CQ
00093         ExecUnitIF* execUnit = op->GetExecUnit();
00094         int latencyCount = execUnit->GetLatencyCount(opClass);
00095         
00096         if( opClass.IsLoad() ){
00097 
00098             static const int MAX_PRED_LEVEL = LatPredResult::MAX_COUNT;
00099             ASSERT( latencyCount <= MAX_PRED_LEVEL, "Make MAX_PRED_LEVEL large enough." );
00100             result.SetCount( latencyCount ); 
00101 
00102             // Get latencies
00103             int latencies[ MAX_PRED_LEVEL ];
00104             for( int i = 0; i < latencyCount; ++i ){
00105                 latencies[i] = execUnit->GetLatency( opClass, i );
00106             }
00107             
00108             // L1 prediction
00109             bool lv1Hit = m_hmPredictor->Predict( op );
00110             result.Set( 0, latencies[0], lv1Hit );
00111             
00112             // Issue latency
00113             int issueLatency = op->GetScheduler()->GetIssueLatency();
00114 
00115             // Lv2 & higher caches are predicted as always hit.
00116             bool prevLevelWokeup = lv1Hit;
00117             for( int i = 1; i < latencyCount; ++i ){
00118 
00119                 // 0  1  2  3  4  5  6  7  8                  
00120                 // SC IS IS IS IS L1 L2 L2 L2
00121                 //             SC IS IS IS IS EX
00122                 //                ^^ L1 miss detected point
00123                 //                   SC IS IS IS IS EX
00124                 // detected     : 1(SC) + 4(IS) + 1(L1)
00125                 // second issue: 1(SC) + L2(3)
00126                 // second issue - detected = L2 - IS - L1
00127 
00128                 int wakeupTime = latencies[i];
00129                 if( prevLevelWokeup ){
00130                     int detectTime = issueLatency + latencies[i - 1] + 1 + 1;// + rescheduling + select
00131                     if( wakeupTime < detectTime ){
00132                         wakeupTime = detectTime;
00133                     }
00134                 }
00135                 result.Set( i, wakeupTime, true );
00136                 prevLevelWokeup = true;
00137             }
00138 
00139             // A last level memory is predicted as always miss and does not wakeup.
00140             if( latencyCount > 1 ){
00141                 result.Set( 
00142                     latencyCount - 1, 
00143                     latencies[latencyCount - 1], 
00144                     false 
00145                 );
00146             }
00147 
00148 
00149         }   // if(opClass.IsLoad()) {
00150         else{
00151             
00152             ASSERT( latencyCount == 1, "A variable latency is not supported except case of Load." );
00153 
00154             int latency = execUnit->GetLatency( opClass, 0 );
00155 
00156             result.SetCount( 1 );
00157             result.Set( 0, latency, true );
00158         }
00159 
00160         op->SetLatPredRsult( result );
00161     }
00162     else {
00163         s_latencyPredictionHook.Trigger(op, this, HookType::HOOK_AROUND);
00164     }
00165 
00166     s_latencyPredictionHook.Trigger(op, this, HookType::HOOK_AFTER);
00167 
00168 }
00169 
00170 //
00171 // predictionHit : CeV\I(L1qbg)
00172 //
00173 void LatPred::Commit( OpIterator op )
00174 {
00175     if( !op->GetOpClass().IsLoad() ){
00176         return;
00177     }
00178 
00179     int latency = op->GetIssueState().executionLatency;
00180     const LatPredResult& latPredResult = 
00181         op->GetLatPredRsult();
00182     const LatPredResult::Scheduling& predSched = latPredResult.Get(0);
00183     
00184     bool predictedAsHitLv1 = predSched.wakeup;
00185     bool hitMissOfLV1      = latency == predSched.latency ? true : false;
00186     if( hitMissOfLV1 ){
00187         if( predictedAsHitLv1 ){
00188             m_numLoadHitPredToHit++;
00189         } 
00190         else{
00191             m_numLoadHitPredToMiss++;
00192         }
00193     }
00194     else{
00195         if( predictedAsHitLv1 ){
00196             m_numLoadMissPredToHit++;
00197         } else {
00198             m_numLoadMissPredToMiss++;
00199         }
00200     }
00201 
00202     if( predictedAsHitLv1 == hitMissOfLV1 )
00203         m_numHit++;
00204     else
00205         m_numMiss++;
00206 
00207     m_hmPredictor->Commit( op, hitMissOfLV1 );
00208 }
00209 
00210 void LatPred::Finished( OpIterator op )
00211 {
00212     if( !op->GetOpClass().IsLoad() ){
00213         return;
00214     }
00215 
00216     int latency = op->GetIssueState().executionLatency;
00217     const LatPredResult::Scheduling& predSched = op->GetLatPredRsult().Get(0);
00218     bool hitMissOfLV1      = latency == predSched.latency ? true : false;
00219     m_hmPredictor->Finished( op, hitMissOfLV1 );
00220 }
00221 
00222 /*
00223 
00224 --- CeV\XPW[Of
00225 
00226 CeV\s(Ip:producer)C\s
00227 (Ic:consumer)XPW[D
00228 
00229 F
00230     Ip: load r1 = [A]
00231     Ic: add  r2 = r1 + 4
00232 
00233 CIp LbV~X\l
00234 _Ip Ic XPW[
00235 
00236     time: 0  1  2  3  4  5  6  7  8
00237     --------------------------------
00238     Ip:   S  I  R  1  2  2  2  W
00239     Ic:   S  S  S  S  S  I  R  X  W
00240 
00241     S : Scheduling
00242     R : Register Read
00243     1 : L1 access
00244     2 : L2 access
00245     X : execute
00246     W : Register Write
00247 
00248     Issue latency : 1cycle
00249     L1 latency    : 1cycle
00250     L2 latency    : 3cycle
00251 
00252 
00253 CeV\sタsIiqbg/~Xj
00254 {IタsIsD
00255 Ip 6cycle ~tH[fBO|[gA7cycle WX^
00256 |[gpC|[g\
00257 AタlD
00258 i|[g\CsND
00259 
00260 タn[hEFAC~X\
00261 Ip 2ssタlD
00262 CIp0 ~X3TCN~L2 ANZXJnC
00263 L1 f[^^C~O2Ip1 sD
00264 Ic CIp1 タs`ssD
00265 
00266     time: 0  1  2  3  4  5  6  7  8  9
00267     -----------------------------------
00268     Ip0:  S  I  R  1 (2  2  2) 
00269     Ip1:  .  .  .  .  S  I  R  1  W
00270     Ic:   S  S  S  S  S  S  I  R  X  W
00271 
00272 */

Onikiri2に対してTue Jun 18 14:34:25 2013に生成されました。  doxygen 1.4.7