src/Sim/Op/Op.h

説明を見る。
00001 // 
00002 // Copyright (c) 2005-2008 Kenichi Watanabe.
00003 // Copyright (c) 2005-2008 Yasuhiro Watari.
00004 // Copyright (c) 2005-2008 Hironori Ichibayashi.
00005 // Copyright (c) 2008-2009 Kazuo Horio.
00006 // Copyright (c) 2009-2013 Naruki Kurata.
00007 // Copyright (c) 2005-2013 Ryota Shioya.
00008 // Copyright (c) 2005-2013 Masahiro Goshima.
00009 // 
00010 // This software is provided 'as-is', without any express or implied
00011 // warranty. In no event will the authors be held liable for any damages
00012 // arising from the use of this software.
00013 // 
00014 // Permission is granted to anyone to use this software for any purpose,
00015 // including commercial applications, and to alter it and redistribute it
00016 // freely, subject to the following restrictions:
00017 // 
00018 // 1. The origin of this software must not be misrepresented; you must not
00019 // claim that you wrote the original software. If you use this software
00020 // in a product, an acknowledgment in the product documentation would be
00021 // appreciated but is not required.
00022 // 
00023 // 2. Altered source versions must be plainly marked as such, and must not be
00024 // misrepresented as being the original software.
00025 // 
00026 // 3. This notice may not be removed or altered from any source
00027 // distribution.
00028 // 
00029 // 
00030 
00031 
00032 #ifndef SIM_OP_OP_H
00033 #define SIM_OP_OP_H
00034 
00035 #include "Interface/Addr.h"
00036 #include "Interface/MemIF.h"
00037 #include "Interface/OpStateIF.h"
00038 #include "Interface/OpInfo.h"
00039 
00040 #include "Sim/ISAInfo.h"
00041 
00042 #include "Sim/Foundation/Hook/HookDecl.h"
00043 #include "Sim/Foundation/Event/EventList/EventList.h"
00044 #include "Sim/Foundation/Debug.h"
00045 #include "Sim/Foundation/Resource/ResourceBase.h"
00046 
00047 #include "Sim/Dependency/MemDependency/MemDependency.h"
00048 #include "Sim/Predictor/LatPred/LatPredResult.h"
00049 #include "Sim/Pipeline/Scheduler/IssueState.h"
00050 #include "Sim/Op/OpStatus.h"
00051 #include "Sim/Memory/Cache/CacheTypes.h"
00052 #include "Sim/Recoverer/Exception.h"
00053 
00054 namespace Onikiri
00055 {
00056     class InorderList;
00057     class Core;
00058     class Thread;
00059     class Scheduler;
00060     class Checkpoint;
00061     class TimeWheelBase;
00062     class RegisterFile;
00063     class PhyReg;
00064     class ExecUnitIF;
00065     struct OpInitArgs;
00066 
00067     // NX
00068     class Op :
00069         public OpStateIF,
00070         public LogicalResourceBase
00071     {
00072     public:
00073         static const int UNSET_REG = -1;
00074         static const int MAX_SRC_MEM_NUM = 1;
00075         static const int MAX_DST_MEM_NUM = 1;
00076 
00077         typedef EventList::MaskType EventMask;
00078         static const int EVENT_MASK_DEFAULT        = 1 << EventList::EVENT_MASK_POS_DEFAULT;
00079         static const int EVENT_MASK_WAKEUP_RELATED = 1 << EventList::EVENT_MASK_POS_USER;
00080         static const int EVENT_MASK_ALL            = EventList::EVENT_MASK_ALL;
00081 
00082 
00083         Op(OpIterator iterator);
00084         virtual ~Op();
00085 
00086         // Initialize
00087         void Initialize(const OpInitArgs& args);
00088 
00089         // OpStateIF
00090         virtual PC GetPC() const { return m_pc; }
00091         virtual const u64 GetSrc(const int index) const;
00092         virtual void SetDst(const int index, const u64 value);
00093         virtual const u64 GetDst(const int index) const;
00094         virtual void SetTakenPC(const PC takenPC);
00095         virtual PC GetTakenPC() const;
00096         virtual void SetTaken(const bool taken);
00097         virtual bool GetTaken() const;
00098 
00099         // MemIF
00100         virtual void Read(  MemAccess* access );
00101         virtual void Write( MemAccess* access );
00102 
00103         // Get a pc of a next of.
00104         PC GetNextPC();
00105 
00106         // Returns whether this op is ready to select in an 'index'-th scheduler.
00107         // 'newDeps' is a set of dependencies that will be satisfied.
00108         // You can test whether an op can be selected if 'newDeps' dependencies are 
00109         // satisfied. 'newDeps' argument can be NULL.
00110         bool IsSrcReady( int index, const DependencySet* newDeps = NULL ) const;
00111         
00112         // CxgOp ゥgTimeWheel o^
00113         void AddEvent(
00114             const EventPtr& evnt, 
00115             TimeWheelBase* timeWheel, 
00116             int time, 
00117             EventMask mask = EVENT_MASK_DEFAULT 
00118         );
00119         // Op o^CxgLZ
00120         void CancelEvent( 
00121             EventMask mask = EVENT_MASK_ALL
00122         );
00123 
00124         // Op o^CxgNA
00125         void ClearEvent();
00126         void ClearWakeupEvent();
00127 
00128         // Re-schedule a self.
00129         // This method clears the events and the dependencies.
00130         // This method must be called from Scheduler::Reschedule().
00131         // If you need to re-schedule an op, use Scheduler::Reschedule().
00132         void RescheduleSelf( bool clearIssueState );        
00133 
00134         // タs
00135         void ExecutionBegin();  // Emulation is executed.
00136         void ExecutionEnd();    // Emulation result is written back and update a state.
00137 
00138         // Write execution results to physical registers.
00139         void WriteExecutionResults();   
00140 
00141         // dependency 
00142         void DissolveSrcReg();
00143         void DissolveSrcMem();
00144 
00145         void SetSrcReg(int index, int phyRegNo);
00146         int GetSrcReg(int index);
00147 
00148         void SetDstReg(int index, int phyRegNo);
00149         int GetDstReg(int index);
00150 
00151         int GetDstRegNum() const { return m_dstNum ;}
00152         int GetSrcRegNum() const { return m_srcNum ;}
00153 
00154         PhyReg* GetDstPhyReg(int index) const { return m_dstPhyReg[index]; }
00155 
00156         void SetSrcMem(int index, MemDependencyPtr memDep);
00157         MemDependencyPtr GetSrcMem(int index) const { return m_srcMem[index]; }
00158 
00159         void SetDstMem(int index, MemDependencyPtr dstMem);
00160         MemDependencyPtr GetDstMem(int index) const { return m_dstMem[index]; }
00161 
00162         int GetDstDepNum() const;
00163         Dependency* GetDstDep( int index ) const;
00164 
00165         OpIterator GetFirstConsumer();
00166         void ResetDependency();
00167 
00168         // Op Dispatche ~Xe[W
00169         bool IsDispatched() const
00170         {
00171             OpStatus status = GetStatus();
00172             return ( status >= OpStatus::OS_DISPATCHED && status != OpStatus::OS_NOP );
00173         }
00174 
00175         //
00176         // accessors
00177         //
00178         int GetLocalTID()           const { return m_localTID;             }
00179         OpInfo* const GetOpInfo()   const { return m_opInfo;               }
00180         const OpClass& GetOpClass() const { return *m_opClass;             }
00181 
00182         int GetNo()             const { return m_no; }
00183         u64 GetSerialID()       const { return m_serialID; }                // eXbhSerialID
00184         u64 GetRetireID()       const { return m_retireID; }                
00185         u64 GetGlobalSerialID() const { return m_globalSerialID; }          // RASXbhSerialID
00186 
00187         Thread*         GetThread()         const { return m_thread;      }
00188         Core*           GetCore()           const { return m_core;        }
00189         InorderList*    GetInorderList()    const { return m_inorderList; }
00190 
00191         void SetStatus( OpStatus status )   { m_status = status; }
00192         OpStatus GetStatus() const          { return m_status;   }
00193 
00194         void SetMemAccess( const MemAccess& memAccess ) { m_memAccess = memAccess; }
00195         const MemAccess& GetMemAccess() const           { return m_memAccess;      }
00196 
00197         void SetException( const Exception& exception) { m_exception = exception; }
00198         const Exception& GetException() const          { return m_exception;      }
00199 
00200         void SetCacheAccessResult( const CacheAccessResult& cacheAccessResult )
00201         { m_cacheAccessResult = cacheAccessResult;  }
00202         const CacheAccessResult& GetCacheAccessResult() const             
00203         { return m_cacheAccessResult;               }
00204 
00205         void SetPredPC(const PC predPC) { m_predPC = predPC; }
00206         PC GetPredPC() const            { return m_predPC; }
00207 
00208         void SetBeforeCheckpoint(Checkpoint* checkpoint) { m_beforeCheckpoint = checkpoint; }
00209         Checkpoint* GetBeforeCheckpoint() const          { return m_beforeCheckpoint; }
00210         void SetAfterCheckpoint(Checkpoint* checkpoint)  { m_afterCheckpoint = checkpoint; }
00211         Checkpoint* GetAfterCheckpoint() const           { return m_afterCheckpoint; }
00212 
00213         void SetLatPredRsult( const LatPredResult& result ) { m_latPredResult = result; }
00214         const LatPredResult& GetLatPredRsult() const        { return m_latPredResult;   }
00215         
00216         void SetIssueState( const IssueState& issueState )  { m_issueState = issueState; }
00217         const IssueState& GetIssueState() const             { return m_issueState;       }
00218 
00219         void SetReserveExecUnit( bool reserveExecUnit ) { m_reserveExecUnit = reserveExecUnit;  }
00220         bool GetReserveExecUnit() const                 { return m_reserveExecUnit;             }
00221 
00222         void SetScheduler(Scheduler* scheduler) { m_scheduler = scheduler; }
00223         Scheduler*  GetScheduler()  const       { return m_scheduler; }
00224         ExecUnitIF* GetExecUnit()   const;
00225 
00226         const OpIterator GetIterator() const       { return m_iterator; }
00227 
00228         //
00229         // methods for debugging
00230         //
00231         std::string ToString(int detail = 5, bool valDetail = false, const char* = "\t");
00232 
00233     protected:
00234 
00235         // PC
00236         PC m_pc;
00237         // PC
00238         OpInfo*  m_opInfo;
00239         const OpClass* m_opClass;
00240 
00241         // PCOpA
00242         //  0 1 2 ...
00243         int m_no;
00244 
00245         // Local thread id in each core
00246         int m_localTID;
00247 
00248         // tFb`
00249         u64 m_serialID;
00250         u64 m_globalSerialID;
00251         // ^CA
00252         u64 m_retireID;
00253 
00254         // tFb`RA/Xbh/InorderList
00255         Thread*     m_thread;
00256         Core*           m_core;
00257         InorderList*    m_inorderList;
00258 
00259         // 
00260         OpStatus m_status;
00261 
00262         // ゥ`FbN|Cg
00263         Checkpoint* m_beforeCheckpoint;
00264         Checkpoint* m_afterCheckpoint;
00265 
00266         //  taken PC
00267         PC m_takenPC;
00268         //  taken 
00269         bool m_taken;
00270 
00271         // Memory access
00272         MemAccess   m_memAccess;
00273 
00274         // Cache access result
00275         CacheAccessResult m_cacheAccessResult;
00276 
00277         // Exception
00278         Exception m_exception;
00279 
00280         // \PC
00281         PC m_predPC;
00282 
00283         // fXeBl[VWX^
00284         int m_dstReg[SimISAInfo::MAX_DST_REG_COUNT];
00285         // \[XWX^
00286         int m_srcReg[SimISAInfo::MAX_SRC_REG_COUNT];
00287 
00288         // fXeBl[VW|C^
00289         MemDependencyPtr m_dstMem[MAX_DST_MEM_NUM];
00290         // \[XW|C^
00291         MemDependencyPtr m_srcMem[MAX_SRC_MEM_NUM];
00292 
00293         // Result of latency prediction
00294         LatPredResult m_latPredResult;
00295 
00296         // State of issuing
00297         IssueState m_issueState;
00298 
00299         // Whether reserving an execution unit or not.
00300         bool m_reserveExecUnit;
00301 
00302         // tbVCxg
00303         EventList m_event;
00304 
00305         // ゥXPW[
00306         Scheduler* m_scheduler;
00307 
00308         // WX^t@C
00309         RegisterFile* m_regFile;
00310 
00311         // \[XfBXeBl[V
00312         int m_srcNum;
00313         int m_dstNum;
00314         PhyReg* m_dstPhyReg[SimISAInfo::MAX_DST_REG_COUNT];
00315         PhyReg* m_srcPhyReg[SimISAInfo::MAX_SRC_REG_COUNT];
00316         u64     m_dstResultValue[SimISAInfo::MAX_DST_REG_COUNT];
00317 
00318         OpIterator m_iterator;
00319 
00320         PhyReg* GetPhyReg(int phyRegNo);
00321     };
00322 
00323     class OpHash
00324     {
00325     public:
00326         size_t operator()(const Op* op) const
00327         {
00328             static const size_t rdiv = 0x100000 / sizeof(Op); 
00329             return (size_t)op * rdiv / 0x100000;
00330         }
00331     };
00332 
00333 }; // namespace Onikiri
00334 
00335 #endif // SIM_OP_OP_H
00336 

Onikiri2に対してTue Jun 18 14:34:24 2013に生成されました。  doxygen 1.4.7