src/Sim/Memory/Cache/CacheAccessRequestQueue.h

説明を見る。
00001 // 
00002 // Copyright (c) 2005-2008 Kenichi Watanabe.
00003 // Copyright (c) 2005-2008 Yasuhiro Watari.
00004 // Copyright (c) 2005-2008 Hironori Ichibayashi.
00005 // Copyright (c) 2008-2009 Kazuo Horio.
00006 // Copyright (c) 2009-2013 Naruki Kurata.
00007 // Copyright (c) 2005-2013 Ryota Shioya.
00008 // Copyright (c) 2005-2013 Masahiro Goshima.
00009 // 
00010 // This software is provided 'as-is', without any express or implied
00011 // warranty. In no event will the authors be held liable for any damages
00012 // arising from the use of this software.
00013 // 
00014 // Permission is granted to anyone to use this software for any purpose,
00015 // including commercial applications, and to alter it and redistribute it
00016 // freely, subject to the following restrictions:
00017 // 
00018 // 1. The origin of this software must not be misrepresented; you must not
00019 // claim that you wrote the original software. If you use this software
00020 // in a product, an acknowledgment in the product documentation would be
00021 // appreciated but is not required.
00022 // 
00023 // 2. Altered source versions must be plainly marked as such, and must not be
00024 // misrepresented as being the original software.
00025 // 
00026 // 3. This notice may not be removed or altered from any source
00027 // distribution.
00028 // 
00029 // 
00030 
00031 
00032 #ifndef SIM_MEMORY_CACHE_CACHE_ACCESS_REQUEST_QUEUE_H
00033 #define SIM_MEMORY_CACHE_CACHE_ACCESS_REQUEST_QUEUE_H
00034 
00035 #include "Sim/Memory/Cache/CacheTypes.h"
00036 
00037 namespace Onikiri
00038 {
00039     class Pipeline;
00040 
00041     //
00042     // A queue of cache access requests.
00043     // This queue is for band width simulation of caches/memories.
00044     //
00045     class CacheAccessRequestQueue
00046     {
00047 
00048     public:
00049         typedef CacheAccess          Access;
00050         typedef CacheAccessResult    Result;
00051         typedef CacheAccessEventType EventType;
00052 
00053         // An access state structure.
00054         // See comments in the 'Push' method.
00055         struct AccessState
00056         {
00057             Access access;
00058 
00059             u64  id;                    // serial ID of an access
00060             s64  startTime;             // access start time
00061             s64  endTime;               // access end time
00062             s64  serializingStartTime;  // serializing start time
00063             s64  serializingEndTime;    // serializing end time
00064 
00065             // A notifiee when an access is finished.
00066             CacheAccessNotifieeIF* notifiee;
00067             CacheAccessNotificationParam notification;
00068         };
00069 
00070         typedef pool_list< AccessState > AccessQueue;
00071         typedef AccessQueue::iterator    AccessQueueIterator;
00072 
00073         CacheAccessRequestQueue( 
00074             Pipeline* pipe,
00075             int ports,
00076             int serializedCycles
00077         );
00078 
00079         virtual ~CacheAccessRequestQueue();
00080 
00081         // Returns the size of the access list.
00082         size_t GetSize() const;
00083 
00084         // Push an access to a queue.
00085         // This method returns the latency of an access.
00086         // See more detailed comments in the method definition.
00087         s64 Push( 
00088             const Access& access, 
00089             int m_minLatency,
00090             CacheAccessNotifieeIF* notifiee,
00091             const CacheAccessNotificationParam& notification
00092         );
00093 
00094         void Pop( const CacheAccess& access, AccessQueueIterator target );
00095 
00096         void SetEnabled( bool enabled );
00097 
00098     protected:
00099         
00100         bool m_enabled;
00101         u64 m_currentAccessID;
00102 
00103         // Access queue
00104         AccessQueue m_queue;
00105 
00106         // A pipeline for a connected cache/memory.
00107         Pipeline* m_pipe;
00108 
00109         // The number of ports of a cache.
00110         int m_ports;
00111 
00112         // The number of cycles for each access that uses a cache port exclusively.
00113         int m_serializedCycles;
00114     
00115         // Get a time when a new memory access can start.
00116         s64 GetNextAccessStartableTime();
00117 
00118         // Add an access state to the list.
00119         void PushAccess(
00120             const CacheAccess& access, 
00121             const AccessState& state, 
00122             int latency 
00123         );
00124     };
00125 
00126 }; // namespace Onikiri
00127 
00128 #endif // SIM_MEMORY_CACHE_CACHE_ACCESS_REQUEST_QUEUE_H
00129 

Onikiri2に対してTue Jun 18 14:34:23 2013に生成されました。  doxygen 1.4.7