src/Sim/Memory/Cache/CacheTypes.h

説明を見る。
00001 // 
00002 // Copyright (c) 2005-2008 Kenichi Watanabe.
00003 // Copyright (c) 2005-2008 Yasuhiro Watari.
00004 // Copyright (c) 2005-2008 Hironori Ichibayashi.
00005 // Copyright (c) 2008-2009 Kazuo Horio.
00006 // Copyright (c) 2009-2013 Naruki Kurata.
00007 // Copyright (c) 2005-2013 Ryota Shioya.
00008 // Copyright (c) 2005-2013 Masahiro Goshima.
00009 // 
00010 // This software is provided 'as-is', without any express or implied
00011 // warranty. In no event will the authors be held liable for any damages
00012 // arising from the use of this software.
00013 // 
00014 // Permission is granted to anyone to use this software for any purpose,
00015 // including commercial applications, and to alter it and redistribute it
00016 // freely, subject to the following restrictions:
00017 // 
00018 // 1. The origin of this software must not be misrepresented; you must not
00019 // claim that you wrote the original software. If you use this software
00020 // in a product, an acknowledgment in the product documentation would be
00021 // appreciated but is not required.
00022 // 
00023 // 2. Altered source versions must be plainly marked as such, and must not be
00024 // misrepresented as being the original software.
00025 // 
00026 // 3. This notice may not be removed or altered from any source
00027 // distribution.
00028 // 
00029 // 
00030 
00031 
00032 #ifndef SIM_MEMORY_CACHE_CACHE_TYPES_H
00033 #define SIM_MEMORY_CACHE_CACHE_TYPES_H
00034 
00035 #include "Sim/Op/OpArray/OpArray.h"
00036 #include "Sim/Pipeline/PipelineNodeIF.h"
00037 #include "Sim/Memory/AddrHasher.h"
00038 
00039 namespace Onikiri
00040 {
00041     class Cache;
00042 
00043     struct CacheLineValue
00044     {
00045         // u8 value[64]
00046     };  
00047 
00048     typedef
00049         AdrHasher 
00050         CacheHasher;
00051 
00052     typedef
00053         std::pair<Addr, CacheLineValue> 
00054         CachePair;
00055 
00056     typedef 
00057         shttl::setassoc_table<
00058             CachePair, 
00059             CacheHasher,
00060             shttl::lru_list< Addr, u8 >
00061         >
00062         CacheTable;
00063 
00064 /* For caches with large associativity.
00065     typedef 
00066         shttl::setassoc_table_strage_map< 
00067             shttl::setassoc_table_line_base< CachePair >
00068         >
00069         CacheStrage;
00070     typedef 
00071         shttl::setassoc_table<
00072             CachePair, 
00073             CacheHasher,
00074             shttl::lru_list< Addr, u32 >,
00075             CacheStrage
00076         >
00077         CacheTable;
00078 */
00079 
00080     typedef 
00081         CacheTable::line_type 
00082         CacheLine;
00083 
00084     typedef 
00085         CacheTable::iterator 
00086         CacheTableIterator;
00087 
00088     typedef 
00089         CacheTable::const_iterator 
00090         CacheTableConstIterator;
00091 
00092     // Additional information for cache accesses.
00093     struct CacheAccess : public MemAccess
00094     {
00095         // Cache operation type.
00096         enum OperationType
00097         {
00098             OT_READ,
00099             OT_WRITE,
00100             OT_WRITE_BACK,
00101             OT_READ_FOR_WRITE_ALLOCATE,
00102             OT_PREFETCH
00103         };
00104         OperationType  type;
00105         OpIterator     op;
00106         CacheLineValue lineValue;
00107 
00108         CacheAccess(
00109             const MemAccess& newMem   = MemAccess(), 
00110             OpIterator       op       = OpIterator(),
00111             OperationType    newType  = OT_READ,
00112             CacheLineValue   newLineValue = CacheLineValue()
00113         ) : 
00114             MemAccess( newMem ),
00115             type ( newType ),
00116             op   ( op ),
00117             lineValue( newLineValue )
00118         {
00119         }
00120 
00121         bool IsWirte() const
00122         {
00123             return type == OT_WRITE || type == OT_WRITE_BACK;
00124         }
00125     };
00126 
00127     // Cache access result.
00128     // Read/Write methods returns this structure.
00129     struct CacheAccessResult
00130     {
00131         int  latency;
00132         enum State
00133         {
00134             ST_HIT,
00135             ST_PENDING_HIT,
00136             ST_MISS,
00137             ST_NOT_ACCESSED
00138         };
00139         State  state;
00140         Cache* cache; 
00141 
00142         // 'line' has an iterator of an accessed line on Read/Write.
00143         // On 'Write', this 'line' also indicates a replaced line.
00144         CacheTableIterator line;
00145 
00146         CacheAccessResult( 
00147             int     newLatency = -1, 
00148             State   newState = ST_NOT_ACCESSED, 
00149             Cache*  newCache = NULL,
00150             CacheTableIterator newLine = CacheTableIterator()
00151         ) :
00152             latency( newLatency ),
00153             state  ( newState ),
00154             cache  ( newCache ),
00155             line   ( newLine )
00156         {
00157         }
00158     };
00159 
00160     enum CacheAccessEventType
00161     {
00162         // ~XLbVANZXACPendingAccess D
00163         // AccessFinished タ addr YCfD
00164         CAET_FILL_FROM_NEXT_CACHE_FINISHED,     
00165         CAET_FILL_FROM_MAL_FINISHED,        // From a missed access list
00166 
00167         // The end of accesses
00168         CAET_WRITE_ALLOCATE_FINISHED,
00169         CAET_WRITE_ACCESS_FINISHED,
00170         CAET_READ_ACCESS_FINISHED
00171     };
00172 
00173     struct CacheAccessNotificationParam
00174     {
00175         CacheAccessEventType type;
00176         CacheAccessResult    result;
00177 
00178         CacheAccessNotificationParam(
00179             const CacheAccessEventType newType = CAET_FILL_FROM_NEXT_CACHE_FINISHED,
00180             const CacheAccessResult&   newResult = CacheAccessResult()
00181         ) :
00182             type( newType ),
00183             result( newResult )
00184         {
00185         }
00186     };
00187 
00188     class CacheAccessNotifieeIF
00189     {
00190     public:
00191         virtual ~CacheAccessNotifieeIF(){};
00192 
00193         // PendingAccess eANZXIm
00194         virtual void AccessFinished( 
00195             const CacheAccess&     access, 
00196             const CacheAccessNotificationParam &param 
00197         ) = 0;
00198     };
00199 
00200     // A hook parameter
00201     struct CacheHookParam
00202     {
00203         const CacheAccess*      access;
00204         const Addr*             address;
00205         const CacheTable*       table;
00206         CacheAccessNotifieeIF*  notifiee;
00207         CacheAccessResult       result;
00208         CacheTableConstIterator line;       // A iterator of a touched/replaced line.
00209         bool replaced;
00210         CacheHookParam() : 
00211             access  ( NULL ),
00212             address    ( NULL ),
00213             table   ( NULL ),
00214             notifiee( NULL ),
00215             replaced( false )
00216         {
00217         }
00218     };
00219 
00220 }; // namespace Onikiri
00221 
00222 #endif // __CACHEIF_H__
00223 

Onikiri2に対してTue Jun 18 14:34:23 2013に生成されました。  doxygen 1.4.7