00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038 #ifndef SIM_MEMORY_PREFETCHER_PREFETCHER_BASE_H
00039 #define SIM_MEMORY_PREFETCHER_PREFETCHER_BASE_H
00040
00041 #include "Sim/Memory/Prefetcher/PrefetcherIF.h"
00042 #include "Sim/Memory/Cache/CacheExtraStateTable.h"
00043 #include "Sim/Foundation/Resource/ResourceNode.h"
00044
00045 namespace Onikiri
00046 {
00047 class Cache;
00048
00049 class PrefetcherBase :
00050 public PrefetcherIF,
00051 public CacheAccessNotifieeIF,
00052 public PhysicalResourceNode
00053 {
00054 public:
00055
00056 PrefetcherBase();
00057 virtual ~PrefetcherBase();
00058
00059
00060
00061
00062 virtual void Initialize( InitPhase phase );
00063
00064 BEGIN_PARAM_MAP("")
00065 BEGIN_PARAM_PATH( GetParamPath() )
00066 PARAM_ENTRY( "@EnablePrefetch", m_enabled );
00067 PARAM_ENTRY( "@Name", m_name );
00068 PARAM_ENTRY( "@OffsetBitSize", m_lineBitSize );
00069 END_PARAM_PATH()
00070 BEGIN_PARAM_PATH( GetResultPath() )
00071 PARAM_ENTRY( "@NumPrefetch", m_numPrefetch );
00072 PARAM_ENTRY( "@NumReadHitAccess", m_numReadHitAccess );
00073 PARAM_ENTRY( "@NumReadMissAccess", m_numReadMissAccess );
00074 PARAM_ENTRY( "@NumWriteHitAccess", m_numWriteHitAccess );
00075 PARAM_ENTRY( "@NumWriteMissAccess", m_numWriteMissAccess );
00076 PARAM_ENTRY( "@NumReplacedLine", m_numReplacedLine );
00077 PARAM_ENTRY( "@NumPrefetchedReplacedLine", m_numPrefetchedReplacedLine );
00078 PARAM_ENTRY( "@NumEffectivePrefetchedLine", m_numEffectivePrefetchedReplacedLine );
00079 RESULT_RATE_ENTRY(
00080 "@NumAccuracy",
00081 m_numEffectivePrefetchedReplacedLine ,
00082 m_numPrefetchedReplacedLine
00083 );
00084 END_PARAM_PATH()
00085 END_PARAM_MAP()
00086
00087 BEGIN_RESOURCE_MAP()
00088 RESOURCE_ENTRY( Cache, "target", m_prefetchTarget )
00089 END_RESOURCE_MAP()
00090
00091 virtual void ChangeSimulationMode( SimulationMode mode );
00092
00093
00094
00095
00096
00097
00098 virtual void OnCacheRead( Cache* cache, CacheHookParam* param );
00099
00100
00101 virtual void OnCacheWrite( Cache* cache, CacheHookParam* param );
00102
00103
00104 virtual void OnCacheInvalidation( Cache* cache, CacheHookParam* param );
00105
00106
00107 virtual void OnCacheTableUpdate( Cache* cache, CacheHookParam* param );
00108
00109
00110
00111
00112
00113
00114 virtual void AccessFinished(
00115 const CacheAccess& access,
00116 const CacheAccessNotificationParam& param
00117 );
00118
00119
00120
00121
00122
00123
00124
00125 virtual void OnCacheAccess(
00126 Cache* cache, const CacheAccess& access, bool hit
00127 ) = 0;
00128
00129 protected:
00130 static const size_t MAX_INFLIGHT_PREFETCH_ACCESSES = 256;
00131
00132 String m_name;
00133
00134
00135
00136 Cache* m_prefetchTarget;
00137
00138 bool m_enabled;
00139
00140
00141 int m_lineSize;
00142 int m_lineBitSize;
00143
00144
00145 s64 m_numPrefetch;
00146
00147 s64 m_numReadHitAccess;
00148 s64 m_numReadMissAccess;
00149 s64 m_numWriteHitAccess;
00150 s64 m_numWriteMissAccess;
00151
00152
00153 s64 m_numReplacedLine;
00154
00155
00156 s64 m_numPrefetchedReplacedLine;
00157
00158
00159
00160 s64 m_numEffectivePrefetchedReplacedLine;
00161
00162
00163 SimulationMode m_mode;
00164
00165
00166 struct PrefetchAccess : public CacheAccess
00167 {
00168
00169 int accessdCount;
00170 bool invalidated;
00171
00172 PrefetchAccess( const CacheAccess& cacheAccess = CacheAccess() ) :
00173 CacheAccess( cacheAccess ),
00174 accessdCount( 0 ),
00175 invalidated ( false )
00176 {
00177 }
00178 };
00179 typedef pool_list< PrefetchAccess > AccessList;
00180 AccessList m_accessList;
00181 AccessList::iterator FindPrefetching( const Addr& addr );
00182
00183
00184 struct ExLineState
00185 {
00186 bool valid;
00187 bool prefetched;
00188 bool accessed;
00189 ExLineState() :
00190 valid ( false ),
00191 prefetched( false ),
00192 accessed ( false )
00193 {
00194 }
00195 };
00196 CacheExtraStateTable< ExLineState > m_exLineState;
00197
00198
00199 virtual void UpdateCacheAccessStat( const CacheAccess& access, bool hit );
00200
00201
00202 virtual void IncrementPrefetchNum();
00203
00204
00205 u64 MaskLineOffset( u64 addr );
00206
00207
00208 bool IsPrefetch( const CacheAccess& access );
00209
00210
00211 void Prefetch( const CacheAccess& access );
00212
00213
00214 bool IsAccessFromThisPrefetcher( CacheHookParam* param ) const;
00215 };
00216
00217
00218 };
00219
00220 #endif // SIM_MEMORY_PREFETCHER_PREFETCHER_BASE_H
00221