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00032 #include <pch.h>
00033
00034 #include "Emu/AlphaLinux/Alpha64Converter.h"
00035
00036 #include "Emu/Utility/GenericOperation.h"
00037 #include "Emu/Utility/OpEmulationState.h"
00038
00039 #include "Emu/AlphaLinux/Alpha64Info.h"
00040 #include "Emu/AlphaLinux/Alpha64OpInfo.h"
00041 #include "Emu/AlphaLinux/Alpha64Decoder.h"
00042 #include "Emu/AlphaLinux/AlphaOperation.h"
00043
00044 using namespace std;
00045 using namespace boost;
00046 using namespace Onikiri;
00047 using namespace Onikiri::EmulatorUtility;
00048 using namespace Onikiri::AlphaLinux;
00049 using namespace Onikiri::EmulatorUtility::Operation;
00050 using namespace Onikiri::AlphaLinux::Operation;
00051
00052
00053
00054
00055
00056 namespace {
00057
00058
00059
00060
00061 const u32 MASK_EXACT = 0xffffffff;
00062 const u32 MASK_PAL = 0xffffffff;
00063 const u32 MASK_MEM = 0xfc000000;
00064 const u32 MASK_MEMF = 0xfc00ffff;
00065 const u32 MASK_OPF = 0xfc00ffe0;
00066 const u32 MASK_OPI = 0xfc001fe0;
00067 const u32 MASK_BR = 0xfc000000;
00068 const u32 MASK_JMP = 0xfc00c000;
00069
00070
00071 const u32 PAL_HALT = 0x00000000;
00072 const u32 PAL_CALLSYS = 0x00000083;
00073 const u32 PAL_IMB = 0x00000086;
00074 const u32 PAL_RDUNIQ = 0x0000009e;
00075 const u32 PAL_WRUNIQ = 0x0000009f;
00076 const u32 PAL_GENTRAP = 0x000000aa;
00077 }
00078
00079 #define OPCODE_PAL(c, f) (u32)((c) << 26 | (f))
00080 #define OPCODE_MEM(c) (u32)((c) << 26)
00081 #define OPCODE_MEMF(c, f) (u32)((c) << 26 | (f))
00082 #define OPCODE_JMP(c, f) (u32)((c) << 26 | (f) << 14)
00083 #define OPCODE_BR(c) (u32)((c) << 26)
00084
00085 #define OPCODE_OPI(c, f) (u32)((c) << 26 | (f) << 5)
00086
00087 #define OPCODE_OPIL(c, f) (u32)((c) << 26 | 1 << 12 | (f) << 5)
00088 #define OPCODE_OPF(c, f) (u32)((c) << 26 | (f) << 5)
00089
00090
00091 namespace {
00092
00093
00094
00095
00096
00097
00098 static const int RegTemplateBegin = -20;
00099 static const int RegTemplateEnd = RegTemplateBegin+4-1;
00100 static const int ImmTemplateBegin = -30;
00101 static const int ImmTemplateEnd = ImmTemplateBegin+2-1;
00102
00103 const int R0 = RegTemplateBegin+0;
00104 const int R1 = RegTemplateBegin+1;
00105 const int R2 = RegTemplateBegin+2;
00106
00107 const int I0 = ImmTemplateBegin+0;
00108 const int I1 = ImmTemplateBegin+1;
00109
00110 const int T0 = Alpha64Info::REG_ADDRESS;
00111 const int FPC = Alpha64Info::REG_FPCR;
00112 }
00113
00114 #define ALPHA_DSTOP(n) DstOperand<n>
00115 #define ALPHA_SRCOP(n) SrcOperand<n>
00116 #define ALPHA_SRCOPFLOAT(n) Cast< float, AsFP< double, SrcOperand<n> > >
00117 #define ALPHA_SRCOPDOUBLE(n) AsFP< double, SrcOperand<n> >
00118
00119 #define D0 ALPHA_DSTOP(0)
00120 #define D1 ALPHA_DSTOP(1)
00121 #define S0 ALPHA_SRCOP(0)
00122 #define S1 ALPHA_SRCOP(1)
00123 #define S2 ALPHA_SRCOP(2)
00124 #define S3 ALPHA_SRCOP(3)
00125 #define SF0 ALPHA_SRCOPFLOAT(0)
00126 #define SF1 ALPHA_SRCOPFLOAT(1)
00127 #define SF2 ALPHA_SRCOPFLOAT(2)
00128 #define SF3 ALPHA_SRCOPFLOAT(3)
00129 #define SD0 ALPHA_SRCOPDOUBLE(0)
00130 #define SD1 ALPHA_SRCOPDOUBLE(1)
00131 #define SD2 ALPHA_SRCOPDOUBLE(2)
00132 #define SD3 ALPHA_SRCOPDOUBLE(3)
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142 Alpha64Converter::OpDef Alpha64Converter::m_OpDefUnknown =
00143 {"unknown", MASK_EXACT, 0, 1, {{OpClassCode::UNDEF, {-1, -1}, {I0, -1, -1, -1}, Alpha64Converter::AlphaUnknownOperation}}};
00144
00145
00146
00147 Alpha64Converter::OpDef Alpha64Converter::m_OpDefsBase[] =
00148 {
00149
00150
00151
00152 {"halt", MASK_PAL, OPCODE_PAL(0x00, PAL_HALT), 1, {{OpClassCode::syscall, {-1, -1}, {-1, -1, -1, -1}, AlphaPALHalt}}},
00153 {"imb", MASK_PAL, OPCODE_PAL(0x00, PAL_IMB), 1, {{OpClassCode::syscall, {-1, -1}, {-1, -1, -1, -1}, AlphaPALIMB}}},
00154 {"rduniq", MASK_PAL, OPCODE_PAL(0x00, PAL_RDUNIQ), 1, {{OpClassCode::syscall, { 0, -1}, {-1, -1, -1, -1}, AlphaPALRdUniq}}},
00155 {"wruniq", MASK_PAL, OPCODE_PAL(0x00, PAL_WRUNIQ), 1, {{OpClassCode::syscall, {-1, -1}, {16, -1, -1, -1}, AlphaPALWrUniq}}},
00156 {"gentrap", MASK_PAL, OPCODE_PAL(0x00, PAL_GENTRAP), 1, {{OpClassCode::syscall, {-1, -1}, {-1, -1, -1, -1}, AlphaPALGenTrap}}},
00157
00158
00159 {"callsys", MASK_PAL, OPCODE_PAL(0x00, PAL_CALLSYS), 2, {
00160 {OpClassCode::syscall, {-1, -1}, { 0, 16, 17, -1}, AlphaSyscallSetArg},
00161 {OpClassCode::syscall_branch, { 0, 19}, {18, 19, 20, -1}, AlphaSyscallCore},
00162 }},
00163
00164
00165
00166
00167 {"nop", MASK_EXACT, 0x47ff041f, 1, {{OpClassCode::iNOP, {-1, -1}, {-1, -1, -1, -1}, NoOperation}}},
00168 {"fnop", MASK_EXACT, 0x5fff041f, 1, {{OpClassCode::fNOP, {-1, -1}, {-1, -1, -1, -1}, NoOperation}}},
00169
00170 {"unop", MASK_EXACT, 0x2ffe0000, 1, {{OpClassCode::iNOP, {-1, -1}, {-1, -1, -1, -1}, NoOperation}}},
00171
00172
00173
00174
00175
00176 {"implver", MASK_OPI, OPCODE_OPIL(0x11, 0x6c), 1, {{OpClassCode::syscall, {R0, -1}, {-1, -1, -1, -1}, UndefinedOperation}}},
00177
00178 {"amask", MASK_OPI, OPCODE_OPI(0x11, 0x61), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, UndefinedOperation}}},
00179 {"amask", MASK_OPI, OPCODE_OPIL(0x11, 0x61), 1, {{OpClassCode::iALU, {R0, -1}, {R1, -1, -1, -1}, UndefinedOperation}}},
00180
00181 {"addl", MASK_OPI, OPCODE_OPI(0x10, 0x00), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, SetSext< D0, IntAdd<u32, S0, S1> >}}},
00182 {"addl", MASK_OPI, OPCODE_OPIL(0x10, 0x00), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, SetSext< D0, IntAdd<u32, S0, S1> >}}},
00183
00184 {"subl", MASK_OPI, OPCODE_OPI(0x10, 0x09), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, SetSext< D0, IntSub<u32, S0, S1> >}}},
00185 {"subl", MASK_OPI, OPCODE_OPIL(0x10, 0x09), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, SetSext< D0, IntSub<u32, S0, S1> >}}},
00186
00187 {"addq", MASK_OPI, OPCODE_OPI(0x10, 0x20), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, IntAdd<u64, S0, S1> >}}},
00188 {"addq", MASK_OPI, OPCODE_OPIL(0x10, 0x20), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, IntAdd<u64, S0, S1> >}}},
00189
00190 {"subq", MASK_OPI, OPCODE_OPI(0x10, 0x29), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, IntSub<u64, S0, S1> >}}},
00191 {"subq", MASK_OPI, OPCODE_OPIL(0x10, 0x29), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, IntSub<u64, S0, S1> >}}},
00192
00193 {"cmpeq", MASK_OPI, OPCODE_OPI(0x10, 0x2d), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaCompare< S0, S1, IntCondEqual<u64> > >}}},
00194 {"cmpeq", MASK_OPI, OPCODE_OPIL(0x10, 0x2d), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaCompare< S0, S1, IntCondEqual<u64> > >}}},
00195
00196 {"cmplt", MASK_OPI, OPCODE_OPI(0x10, 0x4d), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaCompare< S0, S1, IntCondLessSigned<u64> > >}}},
00197 {"cmplt", MASK_OPI, OPCODE_OPIL(0x10, 0x4d), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaCompare< S0, S1, IntCondLessSigned<u64> > >}}},
00198
00199 {"cmple", MASK_OPI, OPCODE_OPI(0x10, 0x6d), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaCompare< S0, S1, IntCondLessEqualSigned<u64> > >}}},
00200 {"cmple", MASK_OPI, OPCODE_OPIL(0x10, 0x6d), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaCompare< S0, S1, IntCondLessEqualSigned<u64> > >}}},
00201
00202 {"cmpult", MASK_OPI, OPCODE_OPI(0x10, 0x1d), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaCompare< S0, S1, IntCondLessUnsigned<u64> > >}}},
00203 {"cmpult", MASK_OPI, OPCODE_OPIL(0x10, 0x1d), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaCompare< S0, S1, IntCondLessUnsigned<u64> > >}}},
00204
00205 {"cmpule", MASK_OPI, OPCODE_OPI(0x10, 0x3d), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaCompare< S0, S1, IntCondLessEqualUnsigned<u64> > >}}},
00206 {"cmpule", MASK_OPI, OPCODE_OPIL(0x10, 0x3d), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaCompare< S0, S1, IntCondLessEqualUnsigned<u64> > >}}},
00207
00208 {"s4addl", MASK_OPI, OPCODE_OPI(0x10, 0x02), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, SetSext< D0, IntScaledAdd< u32, 2, S0, S1> >}}},
00209 {"s4addl", MASK_OPI, OPCODE_OPIL(0x10, 0x02), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, SetSext< D0, IntScaledAdd< u32, 2, S0, S1> >}}},
00210
00211 {"s4addq", MASK_OPI, OPCODE_OPI(0x10, 0x22), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, IntScaledAdd< u64, 2, S0, S1> >}}},
00212 {"s4addq", MASK_OPI, OPCODE_OPIL(0x10, 0x22), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, IntScaledAdd< u64, 2, S0, S1> >}}},
00213
00214 {"s4subl", MASK_OPI, OPCODE_OPI(0x10, 0x0b), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, SetSext< D0, IntScaledSub< u32, 2, S0, S1> >}}},
00215 {"s4subl", MASK_OPI, OPCODE_OPIL(0x10, 0x0b), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, SetSext< D0, IntScaledSub< u32, 2, S0, S1> >}}},
00216
00217 {"s4subq", MASK_OPI, OPCODE_OPI(0x10, 0x2b), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, IntScaledSub< u64, 2, S0, S1> >}}},
00218 {"s4subq", MASK_OPI, OPCODE_OPIL(0x10, 0x2b), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, IntScaledSub< u64, 2, S0, S1> >}}},
00219
00220 {"s8addl", MASK_OPI, OPCODE_OPI(0x10, 0x12), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, SetSext< D0, IntScaledAdd< u32, 3, S0, S1> >}}},
00221 {"s8addl", MASK_OPI, OPCODE_OPIL(0x10, 0x12), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, SetSext< D0, IntScaledAdd< u32, 3, S0, S1> >}}},
00222
00223 {"s8addq", MASK_OPI, OPCODE_OPI(0x10, 0x32), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, IntScaledAdd< u64, 3, S0, S1> >}}},
00224 {"s8addq", MASK_OPI, OPCODE_OPIL(0x10, 0x32), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, IntScaledAdd< u64, 3, S0, S1> >}}},
00225
00226 {"s8subl", MASK_OPI, OPCODE_OPI(0x10, 0x1b), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, SetSext< D0, IntScaledSub< u32, 3, S0, S1> >}}},
00227 {"s8subl", MASK_OPI, OPCODE_OPIL(0x10, 0x1b), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, SetSext< D0, IntScaledSub< u32, 3, S0, S1> >}}},
00228
00229 {"s8subq", MASK_OPI, OPCODE_OPI(0x10, 0x3b), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, IntScaledSub< u64, 3, S0, S1> >}}},
00230 {"s8subq", MASK_OPI, OPCODE_OPIL(0x10, 0x3b), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, IntScaledSub< u64, 3, S0, S1> >}}},
00231
00232
00233
00234 {"mull", MASK_OPI, OPCODE_OPI(0x13, 0x00), 1, {{OpClassCode::iMUL, {R0, -1}, {R1, R2, -1, -1}, SetSext< D0, IntMul<u32, S0, S1> >}}},
00235 {"mull", MASK_OPI, OPCODE_OPIL(0x13, 0x00), 1, {{OpClassCode::iMUL, {R0, -1}, {R1, I0, -1, -1}, SetSext< D0, IntMul<u32, S0, S1> >}}},
00236
00237 {"mulq", MASK_OPI, OPCODE_OPI(0x13, 0x20), 1, {{OpClassCode::iMUL, {R0, -1}, {R1, R2, -1, -1}, Set< D0, IntMul<u64, S0, S1> >}}},
00238 {"mulq", MASK_OPI, OPCODE_OPIL(0x13, 0x20), 1, {{OpClassCode::iMUL, {R0, -1}, {R1, I0, -1, -1}, Set< D0, IntMul<u64, S0, S1> >}}},
00239
00240 {"umulh", MASK_OPI, OPCODE_OPI(0x13, 0x30), 1, {{OpClassCode::iMUL, {R0, -1}, {R1, R2, -1, -1}, Set< D0, IntUMulh64< S0, S1 > >}}},
00241 {"umulh", MASK_OPI, OPCODE_OPIL(0x13, 0x30), 1, {{OpClassCode::iMUL, {R0, -1}, {R1, I0, -1, -1}, Set< D0, IntUMulh64< S0, S1 > >}}},
00242
00243
00244 {"cmoveq", MASK_OPI, OPCODE_OPI(0x11, 0x24), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondEqual<u64> >, S2, S1 > >}}},
00245 {"cmoveq", MASK_OPI, OPCODE_OPIL(0x11, 0x24), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, I0, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondEqual<u64> >, S2, S1 > >}}},
00246
00247 {"cmovlt", MASK_OPI, OPCODE_OPI(0x11, 0x44), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondLessSigned<u64> >, S2, S1 > >}}},
00248 {"cmovlt", MASK_OPI, OPCODE_OPIL(0x11, 0x44), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, I0, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondLessSigned<u64> >, S2, S1 > >}}},
00249
00250 {"cmovle", MASK_OPI, OPCODE_OPI(0x11, 0x64), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondLessEqualSigned<u64> >, S2, S1 > >}}},
00251 {"cmovle", MASK_OPI, OPCODE_OPIL(0x11, 0x64), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, I0, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondLessEqualSigned<u64> >, S2, S1 > >}}},
00252
00253 {"cmovne", MASK_OPI, OPCODE_OPI(0x11, 0x26), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondNotEqual<u64> >, S2, S1 > >}}},
00254 {"cmovne", MASK_OPI, OPCODE_OPIL(0x11, 0x26), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, I0, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondNotEqual<u64> >, S2, S1 > >}}},
00255
00256 {"cmovge", MASK_OPI, OPCODE_OPI(0x11, 0x46), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondGreaterEqualSigned<u64> >, S2, S1 > >}}},
00257 {"cmovge", MASK_OPI, OPCODE_OPIL(0x11, 0x46), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, I0, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondGreaterEqualSigned<u64> >, S2, S1 > >}}},
00258
00259 {"cmovgt", MASK_OPI, OPCODE_OPI(0x11, 0x66), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondGreaterSigned<u64> >, S2, S1 > >}}},
00260 {"cmovgt", MASK_OPI, OPCODE_OPIL(0x11, 0x66), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, I0, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondGreaterSigned<u64> >, S2, S1 > >}}},
00261
00262 {"cmovlbs", MASK_OPI, OPCODE_OPI(0x11, 0x14), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondNotEqualNthBit<u64,0> >, S2, S1 > >}}},
00263 {"cmovlbs", MASK_OPI, OPCODE_OPIL(0x11, 0x14), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, I0, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondNotEqualNthBit<u64,0> >, S2, S1 > >}}},
00264
00265 {"cmovlbc", MASK_OPI, OPCODE_OPI(0x11, 0x16), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondEqualNthBit<u64,0> >, S2, S1 > >}}},
00266 {"cmovlbc", MASK_OPI, OPCODE_OPIL(0x11, 0x16), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R0, I0, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, IntCondEqualNthBit<u64,0> >, S2, S1 > >}}},
00267
00268
00269 {"and", MASK_OPI, OPCODE_OPI(0x11, 0x00), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, BitAnd< u64, S0, S1 > >}}},
00270 {"and", MASK_OPI, OPCODE_OPIL(0x11, 0x00), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, BitAnd< u64, S0, S1 > >}}},
00271
00272 {"bis", MASK_OPI, OPCODE_OPI(0x11, 0x20), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, BitOr< u64, S0, S1 > >}}},
00273 {"bis", MASK_OPI, OPCODE_OPIL(0x11, 0x20), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, BitOr< u64, S0, S1 > >}}},
00274
00275 {"xor", MASK_OPI, OPCODE_OPI(0x11, 0x40), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, BitXor< u64, S0, S1 > >}}},
00276 {"xor", MASK_OPI, OPCODE_OPIL(0x11, 0x40), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, BitXor< u64, S0, S1 > >}}},
00277
00278 {"bic", MASK_OPI, OPCODE_OPI(0x11, 0x08), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, BitAndNot< u64, S0, S1 > >}}},
00279 {"bic", MASK_OPI, OPCODE_OPIL(0x11, 0x08), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, BitAndNot< u64, S0, S1 > >}}},
00280
00281 {"ornot", MASK_OPI, OPCODE_OPI(0x11, 0x28), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, BitOrNot< u64, S0, S1 > >}}},
00282 {"ornot", MASK_OPI, OPCODE_OPIL(0x11, 0x28), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, BitOrNot< u64, S0, S1 > >}}},
00283
00284 {"eqv", MASK_OPI, OPCODE_OPI(0x11, 0x48), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, BitXorNot< u64, S0, S1 > >}}},
00285 {"eqv", MASK_OPI, OPCODE_OPIL(0x11, 0x48), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, BitXorNot< u64, S0, S1 > >}}},
00286
00287 {"sll", MASK_OPI, OPCODE_OPI(0x12, 0x39), 1, {{OpClassCode::iSFT, {R0, -1}, {R1, R2, -1, -1}, Set< D0, LShiftL< u64, S0, S1, 0x3f > >}}},
00288 {"sll", MASK_OPI, OPCODE_OPIL(0x12, 0x39), 1, {{OpClassCode::iSFT, {R0, -1}, {R1, I0, -1, -1}, Set< D0, LShiftL< u64, S0, S1, 0x3f > >}}},
00289
00290 {"sra", MASK_OPI, OPCODE_OPI(0x12, 0x3c), 1, {{OpClassCode::iSFT, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AShiftR< u64, S0, S1, 0x3f > >}}},
00291 {"sra", MASK_OPI, OPCODE_OPIL(0x12, 0x3c), 1, {{OpClassCode::iSFT, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AShiftR< u64, S0, S1, 0x3f > >}}},
00292
00293 {"srl", MASK_OPI, OPCODE_OPI(0x12, 0x34), 1, {{OpClassCode::iSFT, {R0, -1}, {R1, R2, -1, -1}, Set< D0, LShiftR< u64, S0, S1, 0x3f > >}}},
00294 {"srl", MASK_OPI, OPCODE_OPIL(0x12, 0x34), 1, {{OpClassCode::iSFT, {R0, -1}, {R1, I0, -1, -1}, Set< D0, LShiftR< u64, S0, S1, 0x3f > >}}},
00295
00296
00297 {"cmpbge", MASK_OPI, OPCODE_OPI(0x10, 0x0f), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaCmpBge< S0, S1 > >}}},
00298 {"cmpbge", MASK_OPI, OPCODE_OPIL(0x10, 0x0f), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaCmpBge< S0, S1 > >}}},
00299
00300 {"extbl", MASK_OPI, OPCODE_OPI(0x12, 0x06), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaExtxl< u8, S0, S1 > >}}},
00301 {"extbl", MASK_OPI, OPCODE_OPIL(0x12, 0x06), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaExtxl< u8, S0, S1 > >}}},
00302
00303 {"extwl", MASK_OPI, OPCODE_OPI(0x12, 0x16), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaExtxl< u16, S0, S1 > >}}},
00304 {"extwl", MASK_OPI, OPCODE_OPIL(0x12, 0x16), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaExtxl< u16, S0, S1 > >}}},
00305
00306 {"extll", MASK_OPI, OPCODE_OPI(0x12, 0x26), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaExtxl< u32, S0, S1 > >}}},
00307 {"extll", MASK_OPI, OPCODE_OPIL(0x12, 0x26), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaExtxl< u32, S0, S1 > >}}},
00308
00309 {"extql", MASK_OPI, OPCODE_OPI(0x12, 0x36), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaExtxl< u64, S0, S1 > >}}},
00310 {"extql", MASK_OPI, OPCODE_OPIL(0x12, 0x36), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaExtxl< u64, S0, S1 > >}}},
00311
00312 {"extwh", MASK_OPI, OPCODE_OPI(0x12, 0x5a), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaExtxh< u16, S0, S1 > >}}},
00313 {"extwh", MASK_OPI, OPCODE_OPIL(0x12, 0x5a), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaExtxh< u16, S0, S1 > >}}},
00314
00315 {"extlh", MASK_OPI, OPCODE_OPI(0x12, 0x6a), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaExtxh< u32, S0, S1 > >}}},
00316 {"extlh", MASK_OPI, OPCODE_OPIL(0x12, 0x6a), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaExtxh< u32, S0, S1 > >}}},
00317
00318 {"extqh", MASK_OPI, OPCODE_OPI(0x12, 0x7a), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaExtxh< u64, S0, S1 > >}}},
00319 {"extqh", MASK_OPI, OPCODE_OPIL(0x12, 0x7a), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaExtxh< u64, S0, S1 > >}}},
00320
00321 {"insbl", MASK_OPI, OPCODE_OPI(0x12, 0x0b), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaInsxl< u8, S0, S1 > >}}},
00322 {"insbl", MASK_OPI, OPCODE_OPIL(0x12, 0x0b), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaInsxl< u8, S0, S1 > >}}},
00323
00324 {"inswl", MASK_OPI, OPCODE_OPI(0x12, 0x1b), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaInsxl< u16, S0, S1 > >}}},
00325 {"inswl", MASK_OPI, OPCODE_OPIL(0x12, 0x1b), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaInsxl< u16, S0, S1 > >}}},
00326
00327 {"insll", MASK_OPI, OPCODE_OPI(0x12, 0x2b), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaInsxl< u32, S0, S1 > >}}},
00328 {"insll", MASK_OPI, OPCODE_OPIL(0x12, 0x2b), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaInsxl< u32, S0, S1 > >}}},
00329
00330 {"insql", MASK_OPI, OPCODE_OPI(0x12, 0x3b), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaInsxl< u64, S0, S1 > >}}},
00331 {"insql", MASK_OPI, OPCODE_OPIL(0x12, 0x3b), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaInsxl< u64, S0, S1 > >}}},
00332
00333 {"inswh", MASK_OPI, OPCODE_OPI(0x12, 0x57), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaInsxh< u16, S0, S1 > >}}},
00334 {"inswh", MASK_OPI, OPCODE_OPIL(0x12, 0x57), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaInsxh< u16, S0, S1 > >}}},
00335
00336 {"inslh", MASK_OPI, OPCODE_OPI(0x12, 0x67), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaInsxh< u32, S0, S1 > >}}},
00337 {"inslh", MASK_OPI, OPCODE_OPIL(0x12, 0x67), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaInsxh< u32, S0, S1 > >}}},
00338
00339 {"insqh", MASK_OPI, OPCODE_OPI(0x12, 0x77), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaInsxh< u64, S0, S1 > >}}},
00340 {"insqh", MASK_OPI, OPCODE_OPIL(0x12, 0x77), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaInsxh< u64, S0, S1 > >}}},
00341
00342 {"mskbl", MASK_OPI, OPCODE_OPI(0x12, 0x02), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaMskxl< u8, S0, S1 > >}}},
00343 {"mskbl", MASK_OPI, OPCODE_OPIL(0x12, 0x02), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaMskxl< u8, S0, S1 > >}}},
00344
00345 {"mskwl", MASK_OPI, OPCODE_OPI(0x12, 0x12), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaMskxl< u16, S0, S1 > >}}},
00346 {"mskwl", MASK_OPI, OPCODE_OPIL(0x12, 0x12), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaMskxl< u16, S0, S1 > >}}},
00347
00348 {"mskll", MASK_OPI, OPCODE_OPI(0x12, 0x22), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaMskxl< u32, S0, S1 > >}}},
00349 {"mskll", MASK_OPI, OPCODE_OPIL(0x12, 0x22), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaMskxl< u32, S0, S1 > >}}},
00350
00351 {"mskql", MASK_OPI, OPCODE_OPI(0x12, 0x32), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaMskxl< u64, S0, S1 > >}}},
00352 {"mskql", MASK_OPI, OPCODE_OPIL(0x12, 0x32), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaMskxl< u64, S0, S1 > >}}},
00353
00354 {"mskwh", MASK_OPI, OPCODE_OPI(0x12, 0x52), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaMskxh< u16, S0, S1 > >}}},
00355 {"mskwh", MASK_OPI, OPCODE_OPIL(0x12, 0x52), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaMskxh< u16, S0, S1 > >}}},
00356
00357 {"msklh", MASK_OPI, OPCODE_OPI(0x12, 0x62), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaMskxh< u32, S0, S1 > >}}},
00358 {"msklh", MASK_OPI, OPCODE_OPIL(0x12, 0x62), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaMskxh< u32, S0, S1 > >}}},
00359
00360 {"mskqh", MASK_OPI, OPCODE_OPI(0x12, 0x72), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaMskxh< u64, S0, S1 > >}}},
00361 {"mskqh", MASK_OPI, OPCODE_OPIL(0x12, 0x72), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaMskxh< u64, S0, S1 > >}}},
00362
00363 {"zap", MASK_OPI, OPCODE_OPI(0x12, 0x30), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaZap< S0, S1 > >}}},
00364 {"zap", MASK_OPI, OPCODE_OPIL(0x12, 0x30), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaZap< S0, S1 > >}}},
00365
00366 {"zapnot", MASK_OPI, OPCODE_OPI(0x12, 0x31), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaZapNot< S0, S1 > >}}},
00367 {"zapnot", MASK_OPI, OPCODE_OPIL(0x12, 0x31), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaZapNot< S0, S1 > >}}},
00368
00369
00370 {"sextb", MASK_OPI, OPCODE_OPI(0x1c, 0x00), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaSextb< S1 > >}}},
00371 {"sextb", MASK_OPI, OPCODE_OPIL(0x1c, 0x00), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaSextb< S1 > >}}},
00372 {"sextw", MASK_OPI, OPCODE_OPI(0x1c, 0x01), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaSextw< S1 > >}}},
00373 {"sextw", MASK_OPI, OPCODE_OPIL(0x1c, 0x01), 1, {{OpClassCode::iBYTE, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaSextw< S1 > >}}},
00374
00375
00376
00377
00378
00379
00380
00381
00382
00383
00384
00385
00386
00387
00388
00389
00390
00391
00392
00393
00394
00395
00396
00397
00398
00399
00400
00401
00402
00403
00404 {"adds" , MASK_OPF, OPCODE_OPF(0x16, 0x080), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPAdd< float, SF0, SF1, IntConst<int, FE_TONEAREST> > > >}}},
00405 {"adds/su" , MASK_OPF, OPCODE_OPF(0x16, 0x580), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPAdd< float, SF0, SF1, IntConst<int, FE_TONEAREST> > > >}}},
00406 {"adds/suc", MASK_OPF, OPCODE_OPF(0x16, 0x500), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPAdd< float, SF0, SF1, IntConst<int, FE_TOWARDZERO> > > >}}},
00407 {"adds/sum", MASK_OPF, OPCODE_OPF(0x16, 0x540), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPAdd< float, SF0, SF1, IntConst<int, FE_DOWNWARD> > > >}}},
00408 {"adds/sud", MASK_OPF, OPCODE_OPF(0x16, 0x5c0), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2,FPC, -1}, SetFP< D0, Cast< double, FPAdd< float, SF0, SF1, AlphaRoundModeFromFPCR<S2> > > >}}},
00409 {"addt" , MASK_OPF, OPCODE_OPF(0x16, 0x0a0), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPAdd< double, SD0, SD1, IntConst<int, FE_TONEAREST> > >}}},
00410 {"addt/su" , MASK_OPF, OPCODE_OPF(0x16, 0x5a0), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPAdd< double, SD0, SD1, IntConst<int, FE_TONEAREST> > >}}},
00411 {"addt/suc", MASK_OPF, OPCODE_OPF(0x16, 0x520), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPAdd< double, SD0, SD1, IntConst<int, FE_TOWARDZERO> > >}}},
00412 {"addt/sum", MASK_OPF, OPCODE_OPF(0x16, 0x560), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPAdd< double, SD0, SD1, IntConst<int, FE_DOWNWARD> > >}}},
00413 {"addt/sud", MASK_OPF, OPCODE_OPF(0x16, 0x5e0), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2,FPC, -1}, SetFP< D0, FPAdd< double, SD0, SD1, AlphaRoundModeFromFPCR<S2> > >}}},
00414 {"subs" , MASK_OPF, OPCODE_OPF(0x16, 0x081), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPSub< float, SF0, SF1, IntConst<int, FE_TONEAREST> > > >}}},
00415 {"subs/su" , MASK_OPF, OPCODE_OPF(0x16, 0x581), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPSub< float, SF0, SF1, IntConst<int, FE_TONEAREST> > > >}}},
00416 {"subs/suc", MASK_OPF, OPCODE_OPF(0x16, 0x501), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPSub< float, SF0, SF1, IntConst<int, FE_TOWARDZERO> > > >}}},
00417 {"subs/sum", MASK_OPF, OPCODE_OPF(0x16, 0x541), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPSub< float, SF0, SF1, IntConst<int, FE_DOWNWARD> > > >}}},
00418 {"subs/sud", MASK_OPF, OPCODE_OPF(0x16, 0x5c1), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2,FPC, -1}, SetFP< D0, Cast< double, FPSub< float, SF0, SF1 > > >}}},
00419 {"subt" , MASK_OPF, OPCODE_OPF(0x16, 0x0a1), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPSub< double, SD0, SD1, IntConst<int, FE_TONEAREST> > >}}},
00420 {"subt/su" , MASK_OPF, OPCODE_OPF(0x16, 0x5a1), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPSub< double, SD0, SD1, IntConst<int, FE_TONEAREST> > >}}},
00421 {"subt/suc", MASK_OPF, OPCODE_OPF(0x16, 0x521), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPSub< double, SD0, SD1, IntConst<int, FE_TOWARDZERO> > >}}},
00422 {"subt/sum", MASK_OPF, OPCODE_OPF(0x16, 0x561), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPSub< double, SD0, SD1, IntConst<int, FE_DOWNWARD> > >}}},
00423 {"subt/sud", MASK_OPF, OPCODE_OPF(0x16, 0x5e1), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2,FPC, -1}, SetFP< D0, FPSub< double, SD0, SD1, AlphaRoundModeFromFPCR<S2> > >}}},
00424 {"muls" , MASK_OPF, OPCODE_OPF(0x16, 0x082), 1, {{OpClassCode::fMUL, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPMul< float, SF0, SF1, IntConst<int, FE_TONEAREST> > > >}}},
00425 {"muls/su" , MASK_OPF, OPCODE_OPF(0x16, 0x582), 1, {{OpClassCode::fMUL, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPMul< float, SF0, SF1, IntConst<int, FE_TONEAREST> > > >}}},
00426 {"muls/suc" , MASK_OPF, OPCODE_OPF(0x16, 0x502), 1, {{OpClassCode::fMUL, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPMul< float, SF0, SF1, IntConst<int, FE_TOWARDZERO> > > >}}},
00427 {"muls/sum" , MASK_OPF, OPCODE_OPF(0x16, 0x542), 1, {{OpClassCode::fMUL, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPMul< float, SF0, SF1, IntConst<int, FE_DOWNWARD > > > >}}},
00428 {"muls/sud", MASK_OPF, OPCODE_OPF(0x16, 0x5c2), 1, {{OpClassCode::fMUL, {R0, -1}, {R1, R2,FPC, -1}, SetFP< D0, Cast< double, FPMul< float, SF0, SF1, AlphaRoundModeFromFPCR<S2> > > >}}},
00429 {"mult" , MASK_OPF, OPCODE_OPF(0x16, 0x0a2), 1, {{OpClassCode::fMUL, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPMul< double, SD0, SD1, IntConst<int, FE_TONEAREST> > >}}},
00430 {"mult/c" , MASK_OPF, OPCODE_OPF(0x16, 0x022), 1, {{OpClassCode::fMUL, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPMul< double, SD0, SD1, IntConst<int, FE_TOWARDZERO> > >}}},
00431 {"mult/su" , MASK_OPF, OPCODE_OPF(0x16, 0x5a2), 1, {{OpClassCode::fMUL, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPMul< double, SD0, SD1, IntConst<int, FE_TONEAREST> > >}}},
00432 {"mult/suc" , MASK_OPF, OPCODE_OPF(0x16, 0x522), 1, {{OpClassCode::fMUL, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPMul< double, SD0, SD1, IntConst<int, FE_TOWARDZERO> > >}}},
00433 {"mult/sum" , MASK_OPF, OPCODE_OPF(0x16, 0x562), 1, {{OpClassCode::fMUL, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPMul< double, SD0, SD1, IntConst<int, FE_DOWNWARD > > >}}},
00434 {"mult/sud", MASK_OPF, OPCODE_OPF(0x16, 0x5e2), 1, {{OpClassCode::fMUL, {R0, -1}, {R1, R2,FPC, -1}, SetFP< D0, FPMul< double, SD0, SD1, AlphaRoundModeFromFPCR<S2> > >}}},
00435 {"divs" , MASK_OPF, OPCODE_OPF(0x16, 0x083), 1, {{OpClassCode::fDIV, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPDiv< float, SF0, SF1, IntConst<int, FE_TONEAREST> > > >}}},
00436 {"divs/c" , MASK_OPF, OPCODE_OPF(0x16, 0x003), 1, {{OpClassCode::fDIV, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPDiv< float, SF0, SF1, IntConst<int, FE_TOWARDZERO> > > >}}},
00437 {"divs/su" , MASK_OPF, OPCODE_OPF(0x16, 0x583), 1, {{OpClassCode::fDIV, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPDiv< float, SF0, SF1, IntConst<int, FE_TONEAREST> > > >}}},
00438 {"divs/suc" , MASK_OPF, OPCODE_OPF(0x16, 0x503), 1, {{OpClassCode::fDIV, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPDiv< float, SF0, SF1, IntConst<int, FE_TOWARDZERO> > > >}}},
00439 {"divs/sum" , MASK_OPF, OPCODE_OPF(0x16, 0x543), 1, {{OpClassCode::fDIV, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, Cast< double, FPDiv< float, SF0, SF1, IntConst<int, FE_DOWNWARD> > > >}}},
00440 {"divs/sud", MASK_OPF, OPCODE_OPF(0x16, 0x5c3), 1, {{OpClassCode::fDIV, {R0, -1}, {R1, R2,FPC, -1}, SetFP< D0, Cast< double, FPDiv< float, SF0, SF1, AlphaRoundModeFromFPCR<S2> > > >}}},
00441 {"divt" , MASK_OPF, OPCODE_OPF(0x16, 0x0a3), 1, {{OpClassCode::fDIV, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPDiv< double, SD0, SD1, IntConst<int, FE_TONEAREST> > >}}},
00442 {"divt/c" , MASK_OPF, OPCODE_OPF(0x16, 0x023), 1, {{OpClassCode::fDIV, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPDiv< double, SD0, SD1, IntConst<int, FE_TOWARDZERO> > >}}},
00443 {"divt/su" , MASK_OPF, OPCODE_OPF(0x16, 0x5a3), 1, {{OpClassCode::fDIV, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPDiv< double, SD0, SD1, IntConst<int, FE_TONEAREST> > >}}},
00444 {"divt/suc" , MASK_OPF, OPCODE_OPF(0x16, 0x523), 1, {{OpClassCode::fDIV, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPDiv< double, SD0, SD1, IntConst<int, FE_TOWARDZERO> > >}}},
00445 {"divt/sum" , MASK_OPF, OPCODE_OPF(0x16, 0x563), 1, {{OpClassCode::fDIV, {R0, -1}, {R1, R2, -1, -1}, SetFP< D0, FPDiv< double, SD0, SD1, IntConst<int, FE_DOWNWARD> > >}}},
00446 {"divt/sud", MASK_OPF, OPCODE_OPF(0x16, 0x5e3), 1, {{OpClassCode::fDIV, {R0, -1}, {R1, R2,FPC, -1}, SetFP< D0, FPDiv< double, SD0, SD1, AlphaRoundModeFromFPCR<S2> > >}}},
00447
00448 {"cmpteq", MASK_OPI, OPCODE_OPF(0x16, 0x0a5), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaTFloatCompare< S0, S1, FPCondEqual<f64> > >}}},
00449 {"cmptlt", MASK_OPI, OPCODE_OPF(0x16, 0x0a6), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaTFloatCompare< S0, S1, FPCondLess<f64> > >}}},
00450 {"cmptle", MASK_OPI, OPCODE_OPF(0x16, 0x0a7), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaTFloatCompare< S0, S1, FPCondLessEqual<f64> > >}}},
00451 {"cmptun", MASK_OPI, OPCODE_OPF(0x16, 0x0a4), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaTFloatCompare< S0, S1, AlphaFPCondUnordered<f64> > >}}},
00452 {"cmptun/su", MASK_OPI, OPCODE_OPF(0x16, 0x5a4), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaTFloatCompare< S0, S1, AlphaFPCondUnordered<f64> > >}}},
00453
00454 {"cmpteq/su", MASK_OPI, OPCODE_OPF(0x16, 0x5a5), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaTFloatCompare< S0, S1, FPCondEqual<f64> > >}}},
00455 {"cmptlt/su", MASK_OPI, OPCODE_OPF(0x16, 0x5a6), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaTFloatCompare< S0, S1, FPCondLess<f64> > >}}},
00456 {"cmptle/su", MASK_OPI, OPCODE_OPF(0x16, 0x5a7), 1, {{OpClassCode::fADD, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaTFloatCompare< S0, S1, FPCondLessEqual<f64> > >}}},
00457
00458 {"cvtqs", MASK_OPF, OPCODE_OPF(0x16, 0x0bc), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtQS< S0 > >}}},
00459 {"cvtqs/d", MASK_OPF, OPCODE_OPF(0x16, 0x0fc), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtQS< S0 > >}}},
00460
00461 {"cvtqt", MASK_OPF, OPCODE_OPF(0x16, 0x0be), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtQT< S0 > >}}},
00462 {"cvtqt/m", MASK_OPF, OPCODE_OPF(0x16, 0x07e), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtQT< S0 > >}}},
00463 {"cvtqt/d", MASK_OPF, OPCODE_OPF(0x16, 0x0fe), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtQT< S0 > >}}},
00464 {"cvtts", MASK_OPF, OPCODE_OPF(0x16, 0x0ac), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtTS< S0 > >}}},
00465 {"cvtts/su", MASK_OPF, OPCODE_OPF(0x16, 0x5ac), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtTS< S0 > >}}},
00466 {"cvtts/sud", MASK_OPF, OPCODE_OPF(0x16, 0x5ec), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtTS< S0 > >}}},
00467 {"cvttq/c", MASK_OPF, OPCODE_OPF(0x16, 0x02f), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtTQ_c< S0 > >}}},
00468 {"cvttq/svc", MASK_OPF, OPCODE_OPF(0x16, 0x52f), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtTQ_c< S0 > >}}},
00469 {"cvttq/svm", MASK_OPF, OPCODE_OPF(0x16, 0x56f), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtTQ_m< S0 > >}}},
00470 {"cvttq/svd", MASK_OPF, OPCODE_OPF(0x16, 0x5ef), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtTQ_m< S0 > >}}},
00471
00472
00473
00474 {"cvtst", MASK_OPF, OPCODE_OPF(0x16, 0x2ac), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, FPDoubleCopySign< S0, S0 > >}}},
00475 {"cvtst/s", MASK_OPF, OPCODE_OPF(0x16, 0x6ac), 1, {{OpClassCode::fCONV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, FPDoubleCopySign< S0, S0 > >}}},
00476
00477
00478 {"cpys", MASK_OPF, OPCODE_OPF(0x17, 0x020), 1, {{OpClassCode::fMOV, {R0, -1}, {R1, R2, -1, -1}, Set< D0, FPDoubleCopySign< S0, S1 > >}}},
00479 {"cpysn", MASK_OPF, OPCODE_OPF(0x17, 0x021), 1, {{OpClassCode::fMOV, {R0, -1}, {R1, R2, -1, -1}, Set< D0, FPDoubleCopySignNeg< S0, S1 > >}}},
00480 {"cpyse", MASK_OPF, OPCODE_OPF(0x17, 0x022), 1, {{OpClassCode::fMOV, {R0, -1}, {R1, R2, -1, -1}, Set< D0, FPDoubleCopySignExp< S0, S1 > >}}},
00481
00482 {"cvtlq", MASK_OPF, OPCODE_OPF(0x17, 0x010), 1, {{OpClassCode::fMOV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtLQ< S0 > >}}},
00483 {"cvtql", MASK_OPF, OPCODE_OPF(0x17, 0x030), 1, {{OpClassCode::fMOV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtQL< S0 > >}}},
00484 {"cvtql/v", MASK_OPF, OPCODE_OPF(0x17, 0x130), 1, {{OpClassCode::fMOV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtQL< S0 > >}}},
00485 {"cvtql/sv", MASK_OPF, OPCODE_OPF(0x17, 0x530), 1, {{OpClassCode::fMOV, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaCvtQL< S0 > >}}},
00486
00487 {"mt_fpcr", MASK_OPF, OPCODE_OPF(0x17, 0x024), 1, {{OpClassCode::fMOV, {FPC,-1}, {R0, -1, -1, -1}, Set< D0, S0>}}},
00488 {"mf_fpcr", MASK_OPF, OPCODE_OPF(0x17, 0x025), 1, {{OpClassCode::fMOV, {R0, -1}, {FPC,-1, -1, -1}, Set< D0, S0>}}},
00489
00490 {"fcmoveq", MASK_OPI, OPCODE_OPI(0x17, 0x02a), 1, {{OpClassCode::fMOV, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, FPCondEqual<f64> >, S2, S1 > >}}},
00491 {"fcmovne", MASK_OPI, OPCODE_OPI(0x17, 0x02b), 1, {{OpClassCode::fMOV, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, FPCondNotEqual<f64> >, S2, S1 > >}}},
00492 {"fcmovlt", MASK_OPI, OPCODE_OPI(0x17, 0x02c), 1, {{OpClassCode::fMOV, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, FPCondLess<f64> >, S2, S1 > >}}},
00493 {"fcmovge", MASK_OPI, OPCODE_OPI(0x17, 0x02d), 1, {{OpClassCode::fMOV, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, FPCondGreaterEqual<f64> >, S2, S1 > >}}},
00494 {"fcmovle", MASK_OPI, OPCODE_OPI(0x17, 0x02e), 1, {{OpClassCode::fMOV, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, FPCondLessEqual<f64> >, S2, S1 > >}}},
00495 {"fcmovgt", MASK_OPI, OPCODE_OPI(0x17, 0x02f), 1, {{OpClassCode::fMOV, {R0, -1}, {R1, R0, R2, -1}, Set< D0, Select< u64, Compare<S0, IntConst<u64, 0>, FPCondGreater<f64> >, S2, S1 > >}}},
00496
00497
00498 {"sqrts", MASK_OPF, OPCODE_OPF(0x14, 0x08b), 1, {{OpClassCode::fELEM, {R0, -1}, {R2, -1, -1, -1}, SetFP< D0, Cast< double, FPSqrt< float, SF0, IntConst<int, FE_TONEAREST> > > >}}},
00499 {"sqrts/su", MASK_OPF, OPCODE_OPF(0x14, 0x58b), 1, {{OpClassCode::fELEM, {R0, -1}, {R2, -1, -1, -1}, SetFP< D0, Cast< double, FPSqrt< float, SF0, IntConst<int, FE_TONEAREST> > > >}}},
00500 {"sqrts/suc", MASK_OPF, OPCODE_OPF(0x14, 0x50b), 1, {{OpClassCode::fELEM, {R0, -1}, {R2, -1, -1, -1}, SetFP< D0, Cast< double, FPSqrt< float, SF0, IntConst<int, FE_TOWARDZERO> > > >}}},
00501 {"sqrts/sum", MASK_OPF, OPCODE_OPF(0x14, 0x54b), 1, {{OpClassCode::fELEM, {R0, -1}, {R2, -1, -1, -1}, SetFP< D0, Cast< double, FPSqrt< float, SF0, IntConst<int, FE_DOWNWARD> > > >}}},
00502 {"sqrts/sud", MASK_OPF, OPCODE_OPF(0x14, 0x5cb), 1, {{OpClassCode::fELEM, {R0, -1}, {R2, FPC, -1, -1}, SetFP< D0, Cast< double, FPSqrt< float, SF0, AlphaRoundModeFromFPCR<S1> > > >}}},
00503 {"sqrtt", MASK_OPF, OPCODE_OPF(0x14, 0x0ab), 1, {{OpClassCode::fELEM, {R0, -1}, {R2, -1, -1, -1}, SetFP< D0, FPSqrt< double, SD0, IntConst<int, FE_TONEAREST> > >}}},
00504 {"sqrtt/su", MASK_OPF, OPCODE_OPF(0x14, 0x5ab), 1, {{OpClassCode::fELEM, {R0, -1}, {R2, -1, -1, -1}, SetFP< D0, FPSqrt< double, SD0, IntConst<int, FE_TONEAREST> > >}}},
00505 {"sqrtt/suc", MASK_OPF, OPCODE_OPF(0x14, 0x52b), 1, {{OpClassCode::fELEM, {R0, -1}, {R2, -1, -1, -1}, SetFP< D0, FPSqrt< double, SD0, IntConst<int, FE_TOWARDZERO> > >}}},
00506 {"sqrtt/sum", MASK_OPF, OPCODE_OPF(0x14, 0x56b), 1, {{OpClassCode::fELEM, {R0, -1}, {R2, -1, -1, -1}, SetFP< D0, FPSqrt< double, SD0, IntConst<int, FE_DOWNWARD> > >}}},
00507 {"sqrtt/sud", MASK_OPF, OPCODE_OPF(0x14, 0x5eb), 1, {{OpClassCode::fELEM, {R0, -1}, {R2, FPC, -1, -1}, SetFP< D0, FPSqrt< double, SD0, AlphaRoundModeFromFPCR<S1> > >}}},
00508 {"ftois", MASK_OPF, OPCODE_OPF(0x1c, 0x078), 1, {{OpClassCode::ifCONV, {R0, -1}, {R1, -1, -1, -1}, Set< D0, Cast< s64, AlphaFtois<S0> > >}}},
00509 {"ftoit", MASK_OPF, OPCODE_OPF(0x1c, 0x070), 1, {{OpClassCode::ifCONV, {R0, -1}, {R1, -1, -1, -1}, Set< D0, S0 >}}},
00510 {"itofs", MASK_OPF, OPCODE_OPF(0x14, 0x004), 1, {{OpClassCode::ifCONV, {R0, -1}, {R1, -1, -1, -1}, Set< D0, AlphaItofs<S0> >}}},
00511 {"itoft", MASK_OPF, OPCODE_OPF(0x14, 0x024), 1, {{OpClassCode::ifCONV, {R0, -1}, {R1, -1, -1, -1}, Set< D0, S0 >}}},
00512
00513
00514 {"ctlz", MASK_OPI, OPCODE_OPI(0x1c, 0x32), 1, {{OpClassCode::iALU, {R0, -1}, {R2, -1, -1, -1}, Set< D0, NumberOfLeadingZeros<u64, S0> >}}},
00515 {"ctpop", MASK_OPI, OPCODE_OPI(0x1c, 0x30), 1, {{OpClassCode::iALU, {R0, -1}, {R2, -1, -1, -1}, Set< D0, NumberOfPopulations<u64, S0> >}}},
00516 {"cttz", MASK_OPI, OPCODE_OPI(0x1c, 0x33), 1, {{OpClassCode::iALU, {R0, -1}, {R2, -1, -1, -1}, Set< D0, NumberOfTrailingZeros<u64, S0> >}}},
00517
00518
00519 {"pklb", MASK_OPI, OPCODE_OPI(0x1c, 0x37), 1, {{OpClassCode::iALU, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaPackLongWords<S0> >}}},
00520 {"pkwb", MASK_OPI, OPCODE_OPI(0x1c, 0x36), 1, {{OpClassCode::iALU, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaPackWords<S0> >}}},
00521 {"unpkbl", MASK_OPI, OPCODE_OPI(0x1c, 0x35), 1, {{OpClassCode::iALU, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaUnpackLongWords<S0> >}}},
00522 {"unpkbw", MASK_OPI, OPCODE_OPI(0x1c, 0x34), 1, {{OpClassCode::iALU, {R0, -1}, {R2, -1, -1, -1}, Set< D0, AlphaUnpackWords<S0> >}}},
00523 {"minub8", MASK_OPI, OPCODE_OPI(0x1c, 0x3a), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaVectorMin<u8,S0,S1> >}}},
00524 {"minub8i", MASK_OPI, OPCODE_OPIL(0x1c, 0x3a), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaVectorMin<u8,S0,S1> >}}},
00525 {"minsb8", MASK_OPI, OPCODE_OPI(0x1c, 0x38), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaVectorMin<s8,S0,S1> >}}},
00526 {"minsb8i", MASK_OPI, OPCODE_OPIL(0x1c, 0x38), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaVectorMin<s8,S0,S1> >}}},
00527 {"minuw4", MASK_OPI, OPCODE_OPI(0x1c, 0x3b), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaVectorMin<u16,S0,S1> >}}},
00528 {"minuw4i", MASK_OPI, OPCODE_OPIL(0x1c, 0x3b), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaVectorMin<u16,S0,S1> >}}},
00529 {"minsw4", MASK_OPI, OPCODE_OPI(0x1c, 0x39), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaVectorMin<s16,S0,S1> >}}},
00530 {"minsw4i", MASK_OPI, OPCODE_OPIL(0x1c, 0x39), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaVectorMin<s16,S0,S1> >}}},
00531 {"maxub8", MASK_OPI, OPCODE_OPI(0x1c, 0x3c), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaVectorMax<u8,S0,S1> >}}},
00532 {"maxub8i", MASK_OPI, OPCODE_OPIL(0x1c, 0x3c), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaVectorMax<u8,S0,S1> >}}},
00533 {"maxsb8", MASK_OPI, OPCODE_OPI(0x1c, 0x3e), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaVectorMax<s8,S0,S1> >}}},
00534 {"maxsb8i", MASK_OPI, OPCODE_OPIL(0x1c, 0x3e), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaVectorMax<s8,S0,S1> >}}},
00535 {"maxuw4", MASK_OPI, OPCODE_OPI(0x1c, 0x3d), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaVectorMax<u16,S0,S1> >}}},
00536 {"maxuw4i", MASK_OPI, OPCODE_OPIL(0x1c, 0x3d), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaVectorMax<u16,S0,S1> >}}},
00537 {"maxsw4", MASK_OPI, OPCODE_OPI(0x1c, 0x3f), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaVectorMax<s16,S0,S1> >}}},
00538 {"maxsw4i", MASK_OPI, OPCODE_OPIL(0x1c, 0x3f), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaVectorMax<s16,S0,S1> >}}},
00539 {"perr", MASK_OPI, OPCODE_OPI(0x1c, 0x31), 1, {{OpClassCode::iALU, {R0, -1}, {R1, R2, -1, -1}, Set< D0, AlphaPixelError<S0,S1> >}}},
00540
00541
00542
00543
00544
00545 {"trapb", MASK_JMP, OPCODE_MEMF(0x18, 0x0000), 1, {{OpClassCode::iNOP, {-1, -1}, {-1, -1, -1, -1}, NoOperation}}},
00546
00547 {"mb", MASK_JMP, OPCODE_MEMF(0x18, 0x4000), 1, {{OpClassCode::iNOP, {-1, -1}, {-1, -1, -1, -1}, NoOperation}}},
00548 {"wmb", MASK_JMP, OPCODE_MEMF(0x18, 0x4400), 1, {{OpClassCode::iNOP, {-1, -1}, {-1, -1, -1, -1}, NoOperation}}},
00549
00550
00551
00552 {"excb", MASK_JMP, OPCODE_MEMF(0x18, 0x0400), 1, {{OpClassCode::iNOP, {-1, -1}, {-1, -1, -1, -1}, NoOperation}}},
00553
00554 {"rpcc", MASK_JMP, OPCODE_MEMF(0x18, 0xc000), 1, {{OpClassCode::iMOV, {-1, -1}, {-1, -1, -1, -1}, NoOperation}}},
00555
00556
00557 {"jmp", MASK_JMP, OPCODE_JMP(0x1a, 0x0), 1, {{OpClassCode::iJUMP, {R0, -1}, {R1, -1, -1, -1}, CallAbsUncond< D0, S0 >}}},
00558 {"jsr", MASK_JMP, OPCODE_JMP(0x1a, 0x1), 1, {{OpClassCode::CALL_JUMP, {R0, -1}, {R1, -1, -1, -1}, CallAbsUncond< D0, S0 >}}},
00559 {"ret", MASK_JMP, OPCODE_JMP(0x1a, 0x2), 1, {{OpClassCode::RET, {R0, -1}, {R1, -1, -1, -1}, CallAbsUncond< D0, S0 >}}},
00560
00561
00562
00563
00564
00565
00566 {"lda", MASK_MEM, OPCODE_MEM(0x08), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >}}},
00567 {"ldah", MASK_MEM, OPCODE_MEM(0x09), 1, {{OpClassCode::iALU, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaLdah< S0, S1 > >}}},
00568
00569
00570
00571
00572
00573 {"br", MASK_BR, OPCODE_BR(0x30), 1, {{OpClassCode::iBU, {R0, -1}, {I0, -1, -1, -1}, CallRelUncond< D0, S0 >}}},
00574 {"fbeq", MASK_BR, OPCODE_BR(0x31), 1, {{OpClassCode::fBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, FPCondEqual<f64> > >}}},
00575 {"fblt", MASK_BR, OPCODE_BR(0x32), 1, {{OpClassCode::fBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, FPCondLess<f64> > >}}},
00576 {"fble", MASK_BR, OPCODE_BR(0x33), 1, {{OpClassCode::fBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, FPCondLessEqual<f64> > >}}},
00577 {"bsr", MASK_BR, OPCODE_BR(0x34), 1, {{OpClassCode::CALL, {R0, -1}, {I0, -1, -1, -1}, CallRelUncond< D0, S0 >}}},
00578 {"fbne", MASK_BR, OPCODE_BR(0x35), 1, {{OpClassCode::fBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, FPCondNotEqual<f64> > >}}},
00579 {"fbge", MASK_BR, OPCODE_BR(0x36), 1, {{OpClassCode::fBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, FPCondGreaterEqual<f64> > >}}},
00580 {"fbgt", MASK_BR, OPCODE_BR(0x37), 1, {{OpClassCode::fBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, FPCondGreater<f64> > >}}},
00581
00582 {"blbc", MASK_BR, OPCODE_BR(0x38), 1, {{OpClassCode::iBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, IntCondEqualNthBit<u64,0> > >}}},
00583 {"beq", MASK_BR, OPCODE_BR(0x39), 1, {{OpClassCode::iBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, IntCondEqual<u64> > >}}},
00584 {"blt", MASK_BR, OPCODE_BR(0x3a), 1, {{OpClassCode::iBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, IntCondLessSigned<u64> > >}}},
00585 {"ble", MASK_BR, OPCODE_BR(0x3b), 1, {{OpClassCode::iBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, IntCondLessEqualSigned<u64> > >}}},
00586 {"blbs", MASK_BR, OPCODE_BR(0x3c), 1, {{OpClassCode::iBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, IntCondNotEqualNthBit<u64,0> > >}}},
00587 {"bne", MASK_BR, OPCODE_BR(0x3d), 1, {{OpClassCode::iBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, IntCondNotEqual<u64> > >}}},
00588 {"bge", MASK_BR, OPCODE_BR(0x3e), 1, {{OpClassCode::iBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, IntCondGreaterEqualSigned<u64> > >}}},
00589 {"bgt", MASK_BR, OPCODE_BR(0x3f), 1, {{OpClassCode::iBC, {-1, -1}, {R1, I0, -1, -1}, BranchRelCond< S1, Compare< S0, IntConst<u64, 0>, IntCondGreaterSigned<u64> > >}}},
00590
00591 };
00592
00593
00594
00595
00596 Alpha64Converter::OpDef Alpha64Converter::m_OpDefsSplitLoadStore[] =
00597 {
00598 {"ldq_u", MASK_MEM, OPCODE_MEM(0x0b), 2, {
00599 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddrUnaligned< S0, S1 > >},
00600 {OpClassCode::iLD, {R0, -1}, {T0, -1, -1, -1}, Set< D0, Load< u64, S0 > >}
00601 }},
00602 {"stq_u", MASK_MEM, OPCODE_MEM(0x0f), 2, {
00603 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddrUnaligned< S0, S1 > >},
00604 {OpClassCode::iST, {-1, -1}, {R2, T0, -1, -1}, Store< u64, S0, S1 >}
00605 }},
00606
00607 {"ldl", MASK_MEM, OPCODE_MEM(0x28), 2, {
00608 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00609 {OpClassCode::iLD, {R0, -1}, {T0, -1, -1, -1}, SetSext< D0, Load< u32, S0 > >}
00610 }},
00611 {"ldq", MASK_MEM, OPCODE_MEM(0x29), 2, {
00612 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00613 {OpClassCode::iLD, {R0, -1}, {T0, -1, -1, -1}, Set< D0, Load< u64, S0 > >}
00614 }},
00615 {"ldl_l", MASK_MEM, OPCODE_MEM(0x2a), 2, {
00616 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00617 {OpClassCode::iLD, {R0, -1}, {T0, -1, -1, -1}, SetSext< D0, Load< u32, S0 > >}
00618 }},
00619 {"ldq_l", MASK_MEM, OPCODE_MEM(0x2b), 2, {
00620 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00621 {OpClassCode::iLD, {R0, -1}, {T0, -1, -1, -1}, Set< D0, Load< u64, S0 > >}
00622 }},
00623
00624 {"stl", MASK_MEM, OPCODE_MEM(0x2c), 2, {
00625 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00626 {OpClassCode::iST, {-1, -1}, {R2, T0, -1, -1}, Store< u32, S0, S1 >}
00627 }},
00628 {"stq", MASK_MEM, OPCODE_MEM(0x2d), 2, {
00629 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00630 {OpClassCode::iST, {-1, -1}, {R2, T0, -1, -1}, Store< u64, S0, S1 >}
00631 }},
00632 {"stl_c", MASK_MEM, OPCODE_MEM(0x2e), 3, {
00633 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00634 {OpClassCode::iST, {-1, -1}, {R2, T0, -1, -1}, Store< u32, S0, S1 >},
00635
00636 {OpClassCode::iALU, {R2, -1}, {-1, -1, -1, -1}, Set< D0, IntConst<u64, 1> >}
00637 }},
00638 {"stq_c", MASK_MEM, OPCODE_MEM(0x2f), 3, {
00639 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00640 {OpClassCode::iST, {-1, -1}, {R2, T0, -1, -1}, Store< u64, S0, S1 >},
00641
00642 {OpClassCode::iALU, {R2, -1}, {-1, -1, -1, -1}, Set< D0, IntConst<u64, 1> >}
00643 }},
00644
00645
00646
00647 {"lds", MASK_MEM, OPCODE_MEM(0x22), 2, {
00648 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00649 {OpClassCode::fLD, {R0, -1}, {T0, -1, -1, -1}, Set< D0, AlphaLds< S0 > >}
00650 }},
00651 {"ldt", MASK_MEM, OPCODE_MEM(0x23), 2, {
00652 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00653 {OpClassCode::fLD, {R0, -1}, {T0, -1, -1, -1}, Set< D0, Load< u64, S0 > >}
00654 }},
00655 {"sts", MASK_MEM, OPCODE_MEM(0x26), 2, {
00656 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00657 {OpClassCode::fST, {-1, -1}, {R2, T0, -1, -1}, AlphaSts< S0, S1 >}
00658 }},
00659 {"stt", MASK_MEM, OPCODE_MEM(0x27), 2, {
00660 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00661 {OpClassCode::fST, {-1, -1}, {R2, T0, -1, -1}, Store< u64, S0, S1 >}
00662 }},
00663
00664
00665 {"ldbu", MASK_MEM, OPCODE_MEM(0x0a), 2, {
00666 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00667 {OpClassCode::iLD, {R0, -1}, {T0, -1, -1, -1}, Set< D0, Load< u8, S0 > >}
00668 }},
00669 {"ldwu", MASK_MEM, OPCODE_MEM(0x0c), 2, {
00670 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00671 {OpClassCode::iLD, {R0, -1}, {T0, -1, -1, -1}, Set< D0, Load< u16, S0 > >}
00672 }},
00673 {"stb", MASK_MEM, OPCODE_MEM(0x0e), 2, {
00674 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00675 {OpClassCode::iST, {-1, -1}, {R2, T0, -1, -1}, Store< u8, S0, S1 >}
00676 }},
00677 {"stw", MASK_MEM, OPCODE_MEM(0x0d), 2, {
00678 {OpClassCode::ADDR, {T0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaAddr< S0, S1 > >},
00679 {OpClassCode::iST, {-1, -1}, {R2, T0, -1, -1}, Store< u16, S0, S1 >}
00680 }},
00681 };
00682
00683
00684
00685
00686 Alpha64Converter::OpDef Alpha64Converter::m_OpDefsNonSplitLoadStore[] =
00687 {
00688 {"ldq_u", MASK_MEM, OPCODE_MEM(0x0b), 1, {
00689 {OpClassCode::iLD, {R0, -1}, {R1, I0, -1, -1}, Set< D0, Load< u64, AlphaAddrUnaligned< S0, S1 > > >}
00690 }},
00691 {"stq_u", MASK_MEM, OPCODE_MEM(0x0f), 1, {
00692 {OpClassCode::iST, {-1, -1}, {R2, R1, I0, -1}, Store< u64, S0, AlphaAddrUnaligned< S1, S2> >}
00693 }},
00694
00695 {"ldl", MASK_MEM, OPCODE_MEM(0x28), 1, {
00696 {OpClassCode::iLD, {R0, -1}, {R1, I0, -1, -1}, SetSext< D0, Load< u32, AlphaAddr< S0, S1 > > >}
00697 }},
00698 {"ldq", MASK_MEM, OPCODE_MEM(0x29), 1, {
00699 {OpClassCode::iLD, {R0, -1}, {R1, I0, -1, -1}, Set< D0, Load< u64, AlphaAddr< S0, S1 > > >}
00700 }},
00701 {"ldl_l", MASK_MEM, OPCODE_MEM(0x2a), 1, {
00702 {OpClassCode::iLD, {R0, -1}, {R1, I0, -1, -1}, SetSext< D0, Load< u32, AlphaAddr< S0, S1 > > >}
00703 }},
00704 {"ldq_l", MASK_MEM, OPCODE_MEM(0x2b), 1, {
00705 {OpClassCode::iLD, {R0, -1}, {R1, I0, -1, -1}, Set< D0, Load< u64, AlphaAddr< S0, S1 > > >}
00706 }},
00707
00708 {"stl", MASK_MEM, OPCODE_MEM(0x2c), 1, {
00709 {OpClassCode::iST, {-1, -1}, {R2, R1, I0, -1}, Store< u32, S0, AlphaAddr< S1, S2> >}
00710 }},
00711 {"stq", MASK_MEM, OPCODE_MEM(0x2d), 1, {
00712 {OpClassCode::iST, {-1, -1}, {R2, R1, I0, -1}, Store< u64, S0, AlphaAddr< S1, S2> >}
00713 }},
00714 {"stl_c", MASK_MEM, OPCODE_MEM(0x2e), 2, {
00715 {OpClassCode::iST, {-1, -1}, {R2, R1, I0, -1}, Store< u32, S0, AlphaAddr< S1, S2> >},
00716
00717 {OpClassCode::iALU, {R2, -1}, {-1, -1, -1, -1}, Set< D0, IntConst<u64, 1> >}
00718 }},
00719 {"stq_c", MASK_MEM, OPCODE_MEM(0x2f), 2, {
00720 {OpClassCode::iST, {-1, -1}, {R2, R1, I0, -1}, Store< u64, S0, AlphaAddr< S1, S2> >},
00721
00722 {OpClassCode::iALU, {R2, -1}, {-1, -1, -1, -1}, Set< D0, IntConst<u64, 1> >}
00723 }},
00724
00725
00726 {"lds", MASK_MEM, OPCODE_MEM(0x22), 1, {
00727 {OpClassCode::fLD, {R0, -1}, {R1, I0, -1, -1}, Set< D0, AlphaLds< AlphaAddr< S0, S1 > > >}
00728 }},
00729 {"ldt", MASK_MEM, OPCODE_MEM(0x23), 1, {
00730 {OpClassCode::fLD, {R0, -1}, {R1, I0, -1, -1}, Set< D0, Load< u64, AlphaAddr< S0, S1 > > >}
00731 }},
00732 {"sts", MASK_MEM, OPCODE_MEM(0x26), 1, {
00733 {OpClassCode::fST, {-1, -1}, {R2, R1, I0, -1}, AlphaSts< S0, AlphaAddr< S1, S2 > >}
00734 }},
00735 {"stt", MASK_MEM, OPCODE_MEM(0x27), 1, {
00736 {OpClassCode::fST, {-1, -1}, {R2, R1, I0, -1}, Store< u64, S0, AlphaAddr< S1, S2 > >}
00737 }},
00738
00739
00740
00741 {"ldbu", MASK_MEM, OPCODE_MEM(0x0a), 1, {
00742 {OpClassCode::iLD, {R0, -1}, {R1, I0, -1, -1}, Set< D0, Load< u8, AlphaAddr< S0, S1 > > >}
00743 }},
00744 {"ldwu", MASK_MEM, OPCODE_MEM(0x0c), 1, {
00745 {OpClassCode::iLD, {R0, -1}, {R1, I0, -1, -1}, Set< D0, Load< u16, AlphaAddr< S0, S1 > > >}
00746 }},
00747 {"stb", MASK_MEM, OPCODE_MEM(0x0e), 1, {
00748 {OpClassCode::iST, {-1, -1}, {R2, R1, I0, -1}, Store< u8, S0, AlphaAddr< S1, S2> >}
00749 }},
00750 {"stw", MASK_MEM, OPCODE_MEM(0x0d), 1, {
00751 {OpClassCode::iST, {-1, -1}, {R2, R1, I0, -1}, Store< u16, S0, AlphaAddr< S1, S2> >}
00752 }},
00753 };
00754
00755
00756
00757
00758
00759
00760
00761 Alpha64Converter::Alpha64Converter()
00762 {
00763 AddToOpMap(m_OpDefsBase, sizeof(m_OpDefsBase)/sizeof(OpDef));
00764 if (IsSplitLoadStoreEnabled()) {
00765 AddToOpMap(m_OpDefsSplitLoadStore, sizeof(m_OpDefsSplitLoadStore)/sizeof(OpDef));
00766 }
00767 else{
00768 AddToOpMap(m_OpDefsNonSplitLoadStore, sizeof(m_OpDefsNonSplitLoadStore)/sizeof(OpDef));
00769 }
00770 }
00771
00772 Alpha64Converter::~Alpha64Converter()
00773 {
00774 }
00775
00776
00777 std::pair<Alpha64Converter::OperandType, int> Alpha64Converter::GetActualSrcOperand(int srcTemplate, const DecodedInsn& decoded) const
00778 {
00779 typedef std::pair<OperandType, int> RetType;
00780 if (srcTemplate == -1) {
00781 return RetType(OpInfoType::NONE, 0);
00782 }
00783 else if (ImmTemplateBegin <= srcTemplate && srcTemplate <= ImmTemplateEnd) {
00784 return RetType(OpInfoType::IMM, srcTemplate - ImmTemplateBegin);
00785 }
00786 else {
00787 return RetType(OpInfoType::REG, GetActualRegNumber(srcTemplate, decoded) );
00788 }
00789 }
00790
00791
00792 int Alpha64Converter::GetActualRegNumber(int regTemplate, const DecodedInsn& decoded) const
00793 {
00794 if (regTemplate == -1) {
00795 return -1;
00796 }
00797 else if (RegTemplateBegin <= regTemplate && regTemplate <= RegTemplateEnd) {
00798 return decoded.Reg[regTemplate - RegTemplateBegin];
00799 }
00800 else if (0 <= regTemplate && regTemplate < Alpha64Info::RegisterCount) {
00801 return regTemplate;
00802 }
00803 else {
00804 ASSERT(0, "Alpha64Converter Logic Error : invalid regTemplate");
00805 return -1;
00806 }
00807 }
00808
00809
00810 bool Alpha64Converter::IsZeroReg(int regNum) const
00811 {
00812 const int IntZeroReg = 31;
00813 const int FPZeroReg = 63;
00814
00815 return regNum == IntZeroReg || regNum == FPZeroReg;
00816 }
00817
00818
00819 void Alpha64Converter::AlphaUnknownOperation(OpEmulationState* opState)
00820 {
00821 u32 codeWord = static_cast<u32>( SrcOperand<0>()(opState) );
00822
00823 DecoderType decoder;
00824 DecodedInsn decoded;
00825 decoder.Decode( codeWord, &decoded);
00826
00827 stringstream ss;
00828 u32 opcode = (codeWord >> 26) & 0x3f;
00829 ss << "unknown instruction : " << hex << setw(8) << codeWord << endl;
00830 ss << "\topcode : " << hex << opcode << endl;
00831 ss << "\timm[1] : " << hex << decoded.Imm[1] << endl;
00832
00833 THROW_RUNTIME_ERROR(ss.str().c_str());
00834 }
00835
00836 const Alpha64Converter::OpDef* Alpha64Converter::GetOpDefUnknown() const
00837 {
00838 return &m_OpDefUnknown;
00839 }