src/Sim/Memory/MemOrderManager/MemOrderManager.h

説明を見る。
00001 // 
00002 // Copyright (c) 2005-2008 Kenichi Watanabe.
00003 // Copyright (c) 2005-2008 Yasuhiro Watari.
00004 // Copyright (c) 2005-2008 Hironori Ichibayashi.
00005 // Copyright (c) 2008-2009 Kazuo Horio.
00006 // Copyright (c) 2009-2013 Naruki Kurata.
00007 // Copyright (c) 2005-2013 Ryota Shioya.
00008 // Copyright (c) 2005-2013 Masahiro Goshima.
00009 // 
00010 // This software is provided 'as-is', without any express or implied
00011 // warranty. In no event will the authors be held liable for any damages
00012 // arising from the use of this software.
00013 // 
00014 // Permission is granted to anyone to use this software for any purpose,
00015 // including commercial applications, and to alter it and redistribute it
00016 // freely, subject to the following restrictions:
00017 // 
00018 // 1. The origin of this software must not be misrepresented; you must not
00019 // claim that you wrote the original software. If you use this software
00020 // in a product, an acknowledgment in the product documentation would be
00021 // appreciated but is not required.
00022 // 
00023 // 2. Altered source versions must be plainly marked as such, and must not be
00024 // misrepresented as being the original software.
00025 // 
00026 // 3. This notice may not be removed or altered from any source
00027 // distribution.
00028 // 
00029 // 
00030 
00031 
00032 #ifndef SIM_MEMORY_MEM_ORDER_MANAGER_H
00033 #define SIM_MEMORY_MEM_ORDER_MANAGER_H
00034 
00035 #include "Sim/Foundation/Resource/ResourceNode.h"
00036 #include "Env/Param/ParamExchange.h"
00037 #include "Sim/Foundation/Hook/Hook.h"
00038 
00039 #include "Sim/Op/OpContainer/OpList.h"
00040 #include "Sim/Op/OpContainer/OpExtraStateTable.h"
00041 
00042 #include "Sim/Core/DataPredTypes.h"
00043 #include "Sim/Memory/MemOrderManager/MemOrderOperations.h"
00044 
00045 namespace Onikiri 
00046 {
00047     class Core;
00048     class Cache;
00049     class CacheSystem;
00050 
00051     class MemOrderManager :
00052         public PhysicalResourceNode
00053     {
00054 
00055     public:
00056         BEGIN_PARAM_MAP("")
00057             
00058             BEGIN_PARAM_PATH( GetParamPath() )
00059 
00060                 PARAM_ENTRY( "@Unified",         m_unified )
00061                 PARAM_ENTRY( "@UnifiedCapacity", m_unifiedCapacity )
00062                 PARAM_ENTRY( "@LoadCapacity",    m_loadCapacity )
00063                 PARAM_ENTRY( "@StoreCapacity",   m_storeCapacity )
00064                 PARAM_ENTRY( "@IdealPatialLoad", m_idealPartialLoad )
00065                 PARAM_ENTRY( "@RemoveOpsOnCommit",  m_removeOpsOnCommit )
00066                 
00067             END_PARAM_PATH()
00068 
00069             BEGIN_PARAM_PATH( GetResultPath() )
00070 
00071                 BEGIN_PARAM_PATH( "ExecutedLoadAccess" )
00072                     PARAM_ENTRY( "@NumStoreForwarding", m_numExecutedStoreForwarding )
00073                     PARAM_ENTRY( "@NumLoadAccess",      m_numExecutedLoadAccess )
00074                 END_PARAM_PATH()
00075 
00076                 BEGIN_PARAM_PATH( "RetiredLoadAccess" )
00077                     PARAM_ENTRY( "@NumStoreForwarding", m_numRetiredStoreForwarding )
00078                     PARAM_ENTRY( "@NumLoadAccess",      m_numRetiredLoadAccess )
00079                 END_PARAM_PATH()
00080             END_PARAM_PATH()
00081 
00082         END_PARAM_MAP()
00083 
00084         BEGIN_RESOURCE_MAP()
00085             RESOURCE_ENTRY( EmulatorIF,  "emulator", m_emulator )
00086             RESOURCE_ENTRY( Core,        "core",        m_core )
00087             RESOURCE_ENTRY( CacheSystem, "cacheSystem", m_cacheSystem )
00088         END_RESOURCE_MAP()
00089 
00090         MemOrderManager();
00091         virtual ~MemOrderManager();
00092 
00093         virtual void Initialize( InitPhase phase );
00094         virtual void Finalize();
00095 
00096         // numOpAllocate
00097         bool CanAllocate( OpIterator* infoArray, int numOp );
00098 
00099         // fetchGg
00100         void Allocate( OpIterator op );
00101         
00102         // タsI
00103         void Finished( OpIterator op );
00104 
00105         // OpaddressStoreMemOrderManagerOpO
00106         OpIterator GetProducerStore( OpIterator op, const MemAccess& access ) const;
00107 
00108         // Get a finished consumer of a producer store.
00109         // This method is used for detecting access order violation.
00110         // Returns OpIterator(0) if such consumers do not exist.
00111         // 'index' is an index of consumer in program order.
00112         OpIterator GetConsumerLoad( OpIterator producer, const MemAccess& access , int index );
00113 
00114         void Commit( OpIterator op );
00115         void Retire( OpIterator op );
00116         void Flush( OpIterator op );
00117 
00118         // op->Read, Write  Read, Write
00119         // op nKvMemIFp
00120         void Read( OpIterator op, MemAccess* access );
00121         void Write( OpIterator op, MemAccess* access );
00122 
00123         // accessors
00124         MemIF* GetMemImage() const { return m_emulator->GetMemImage();  }
00125         Core*  GetCore()     const { return m_core;                     }
00126         bool   IsIdealPatialLoadEnabled() const { return m_idealPartialLoad; }
00127 
00128         // Hook
00129         struct MemImageAccessParam
00130         {
00131             MemIF*     memImage;
00132             MemAccess* memAccess;
00133         };
00134         typedef HookPoint<MemOrderManager, MemImageAccessParam> MemImageAccessHook;
00135         static MemImageAccessHook s_writeMemImageHook;
00136         static MemImageAccessHook s_readMemImageHook;
00137 
00138     protected:
00139 
00140         typedef DataPredMissRecovery Recovery;
00141 
00142         bool m_unified;             // Unified/dedicated load/store queue(s).
00143         int m_unifiedCapacity;      // MemOrderManager
00144         int m_loadCapacity;         // MemOrderManager
00145         int m_storeCapacity;        // MemOrderManager
00146         bool m_idealPartialLoad;    // Partial load is processed ideally or not.
00147         bool m_removeOpsOnCommit;   // If this parameter is true, ops are removed on commitment,
00148                                     // otherwise ops are removed on retirement.
00149 
00150         int m_cacheLatency; // 1LbVCeV
00151 
00152         // statistic information
00153         s64 m_numExecutedStoreForwarding;   // LoadタsStoreBufferf[^
00154         s64 m_numRetiredStoreForwarding;
00155 
00156         s64 m_numExecutedLoadAccess;        // StoreBufferANZX
00157         s64 m_numRetiredLoadAccess;
00158 
00159         // L1D cache
00160         Cache* m_cache;
00161         CacheSystem* m_cacheSystem;
00162 
00163         // tFb`^CA[hEXgA
00164         OpList m_loadList;
00165         OpList m_storeList;
00166 
00167         Core* m_core;
00168         EmulatorIF* m_emulator;
00169 
00170         // Operations related to detect address intersection.
00171         MemOrderOperations m_memOperations;
00172 
00173         // G~[^C[W
00174         void ReadMemImage( OpIterator op, MemAccess* access );
00175         void WriteMemImage( OpIterator op, MemAccess* access );
00176 
00177         // Detect access order violation between 
00178         // a store executed in this cycle and 
00179         // already executed successor loads on program order.
00180         void DetectAccessOrderViolation( OpIterator store );
00181 
00182         // Detect and recover from partial read violation.
00183         // Returns true if violation is detected.
00184         bool DetectPartialLoadViolation( OpIterator op );
00185 
00186         void Delete( OpIterator op );
00187 
00188     };
00189 }; // namespace Onikiri
00190 
00191 #endif // SIM_MEMORY_MEM_ORDER_MANAGER_H
00192 

Onikiri2に対してTue Jun 18 14:34:24 2013に生成されました。  doxygen 1.4.7