00001 // 00002 // Copyright (c) 2005-2008 Kenichi Watanabe. 00003 // Copyright (c) 2005-2008 Yasuhiro Watari. 00004 // Copyright (c) 2005-2008 Hironori Ichibayashi. 00005 // Copyright (c) 2008-2009 Kazuo Horio. 00006 // Copyright (c) 2009-2013 Naruki Kurata. 00007 // Copyright (c) 2005-2013 Ryota Shioya. 00008 // Copyright (c) 2005-2013 Masahiro Goshima. 00009 // 00010 // This software is provided 'as-is', without any express or implied 00011 // warranty. In no event will the authors be held liable for any damages 00012 // arising from the use of this software. 00013 // 00014 // Permission is granted to anyone to use this software for any purpose, 00015 // including commercial applications, and to alter it and redistribute it 00016 // freely, subject to the following restrictions: 00017 // 00018 // 1. The origin of this software must not be misrepresented; you must not 00019 // claim that you wrote the original software. If you use this software 00020 // in a product, an acknowledgment in the product documentation would be 00021 // appreciated but is not required. 00022 // 00023 // 2. Altered source versions must be plainly marked as such, and must not be 00024 // misrepresented as being the original software. 00025 // 00026 // 3. This notice may not be removed or altered from any source 00027 // distribution. 00028 // 00029 // 00030 00031 00032 #ifndef SIM_MEMORY_CACHE_CACHE_MISSED_ACCESS_LIST_H 00033 #define SIM_MEMORY_CACHE_CACHE_MISSED_ACCESS_LIST_H 00034 00035 #include "Sim/Memory/Cache/CacheTypes.h" 00036 00037 namespace Onikiri 00038 { 00039 class Pipeline; 00040 00041 // 00042 // This class handles missed accesses. 00043 // It corresponds to Miss Status Handling Register(MSHR) 00044 // 00045 class CacheMissedAccessList 00046 { 00047 00048 public: 00049 typedef CacheAccess Access; 00050 typedef CacheAccessResult Result; 00051 typedef CacheAccessEventType EventType; 00052 00053 static const size_t MAX_MISSED_ACCESS_LIST_LIMIT = 1024; 00054 static const size_t MAX_NOTIFIEE_COUNT = 4; 00055 typedef 00056 boost::array<CacheAccessNotifieeIF*, MAX_NOTIFIEE_COUNT> 00057 NotifieeArray; 00058 00059 // An access state structure. 00060 // See comments in'Add' method. 00061 struct AccessState 00062 { 00063 Access access; 00064 00065 u64 id; // serial ID of an access 00066 s64 startTime; // access start time 00067 s64 endTime; // access end time 00068 00069 // true if this entry is a link to a actual access. 00070 // A successor access that hits a predecessor access is 00071 // linked to the predecessor access. 00072 // A link access does not consume a port. 00073 bool link; 00074 00075 // Notifies when missed accesses are finished. 00076 NotifieeArray notifiees; 00077 int notifieesCount; 00078 CacheAccessNotificationParam 00079 notification; 00080 }; 00081 00082 typedef pool_list< AccessState > AccessList; 00083 typedef AccessList::iterator AccessListIterator; 00084 00085 CacheMissedAccessList( 00086 Pipeline* pipe, 00087 int offsetBitSize 00088 ); 00089 00090 virtual ~CacheMissedAccessList(); 00091 00092 Result Find( const Addr& addr ); 00093 00094 // Returns the size of the access list. 00095 size_t GetSize() const; 00096 00097 // Add a missed access to the list. 00098 void Add( 00099 const Access& access, 00100 const Result& result, 00101 CacheAccessNotifieeIF* notifiees[], 00102 int notifieesCount, 00103 const CacheAccessNotificationParam& notification 00104 ); 00105 00106 void Remove( const CacheAccess& access, AccessListIterator target ); 00107 00108 void SetEnabled( bool enabled ); 00109 00110 protected: 00111 00112 bool m_enabled; 00113 00114 u64 m_currentAccessID; 00115 00116 // ANZXANZXXg 00117 AccessList m_list; 00118 00119 // A pipeline for the cache/memory. 00120 Pipeline* m_pipe; 00121 00122 // An address offset of a cache line 00123 int m_offsetBitSize; 00124 00125 Addr MaskLineOffset( Addr addr ); 00126 AccessListIterator FindAccess( const Addr& addr ); 00127 00128 // Add an access state to the list. 00129 void AddList( 00130 const CacheAccess& access, const AccessState& state, int latency 00131 ); 00132 }; 00133 00134 }; // namespace Onikiri 00135 00136 #endif // SIM_MEMORY_CACHE_CACHE_MISSED_ACCESS_LIST_H