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00032 #include <pch.h>
00033
00034 #include "Sim/ExecUnit/MemExecUnit.h"
00035
00036 #include "Sim/Thread/Thread.h"
00037 #include "Sim/Pipeline/Scheduler/Scheduler.h"
00038 #include "Sim/Memory/Cache/Cache.h"
00039 #include "Sim/Memory/Cache/CacheSystem.h"
00040 #include "Sim/Memory/MemOrderManager/MemOrderManager.h"
00041 #include "Sim/Core/Core.h"
00042 #include "Sim/Op/Op.h"
00043 #include "Sim/Pipeline/Pipeline.h"
00044 #include "Sim/ExecUnit/ExecLatencyInfo.h"
00045 #include "Sim/Foundation/Hook/Hook.h"
00046 #include "Sim/InorderList/InorderList.h"
00047 #include "Sim/Recoverer/Recoverer.h"
00048
00049
00050 using namespace std;
00051 using namespace Onikiri;
00052
00053 MemExecUnit::MemExecUnit() :
00054 m_cacheSystem(0),
00055 m_cache(0),
00056 m_cacheCount(0),
00057 m_floatConversionLatency( 0 )
00058 {
00059 }
00060
00061 MemExecUnit::~MemExecUnit()
00062 {
00063 ReleaseParam();
00064 }
00065
00066 void MemExecUnit::Initialize(InitPhase phase)
00067 {
00068 if(phase == INIT_PRE_CONNECTION){
00069 }
00070 else if(phase == INIT_POST_CONNECTION){
00071 CheckNodeInitialized( "memOrderManager", m_memOrderManager );
00072 CheckNodeInitialized( "cacheSystem", m_cacheSystem );
00073
00074
00075 m_cache = m_cacheSystem->GetFirstLevelDataCache();
00076 m_cacheCount = 0;
00077 Cache* cache = m_cache;
00078 for(; cache != 0; cache = cache->GetNextCache(), ++m_cacheCount) {}
00079 }
00080
00081 PipelinedExecUnit::Initialize(phase);
00082
00083 }
00084
00085
00086
00087 void MemExecUnit::Execute( OpIterator op )
00088 {
00089 ExecUnitBase::Execute( op );
00090 RegisterEvents( op, GetExecutedLatency( op ) );
00091 }
00092
00093
00094 int MemExecUnit::GetExecutedLatency( OpIterator op )
00095 {
00096 int latency = 0;
00097
00098 if(op->GetOpClass().IsLoad()) {
00099 latency = GetExecutedReadLatency(op);
00100 } else if(op->GetOpClass().IsStore()) {
00101 latency = GetExecutedWriteLatency(op);
00102 } else {
00103 THROW_RUNTIME_ERROR("Unknwon opclass.");
00104 }
00105
00106 return latency;
00107 }
00108
00109
00110
00111
00112
00113 int MemExecUnit::GetExecutedReadLatency( OpIterator op )
00114 {
00115 int readLatency = 0;
00116
00117
00118
00119 OpIterator producer = GetProducerStore( op );
00120
00121
00122
00123 bool firstAccess =
00124 op->GetCacheAccessResult().state == CacheAccessResult::ST_NOT_ACCESSED;
00125
00126 if( !producer.IsNull() ) {
00127 readLatency = GetLatency( op->GetOpClass(), 0 );
00128
00129 if( firstAccess ){
00130 CacheAccessResult result( 0, CacheAccessResult::ST_HIT, NULL );
00131 op->SetCacheAccessResult( result );
00132 }
00133 }
00134 else {
00135 CacheAccess access( op->GetMemAccess(), op, CacheAccess::OT_READ );
00136 CacheAccessResult result = m_cache->Read( access, NULL );
00137 readLatency = result.latency;
00138
00139 if( firstAccess ){
00140 op->SetCacheAccessResult( result );
00141 }
00142
00143
00144 if( op->GetOpClass().IsFloat() ) {
00145 readLatency += m_floatConversionLatency;
00146 }
00147 }
00148
00149 return readLatency;
00150 }
00151
00152
00153 int MemExecUnit::GetExecutedWriteLatency(OpIterator op)
00154 {
00155
00156 int code = op->GetOpClass().GetCode();
00157 int writeLatency = m_execLatencyInfo->GetLatency(code);
00158
00159 return writeLatency;
00160 }
00161
00162
00163 int MemExecUnit::GetLatencyCount(const OpClass& opClass)
00164 {
00165 ASSERT(opClass.IsMem(), "not mem op");
00166 if( opClass.IsStore() ) {
00167
00168 return 1;
00169 }
00170
00171
00172 return m_cacheCount;
00173 }
00174
00175
00176 int MemExecUnit::GetLatency(const OpClass& opClass, int index)
00177 {
00178 ASSERT( opClass.IsMem(), "not mem op");
00179 if( opClass.IsStore() ) {
00180
00181 return m_execLatencyInfo->GetLatency(opClass.GetCode());
00182 }
00183
00184 int latency = 0;
00185 Cache* cache = m_cache;
00186 for(int i = 0; i <= index; ++i, cache = cache->GetNextCache()) {
00187 ASSERT(cache != 0, "cache not set.(index: %d)", index);
00188 latency += cache->GetStaticLatency();
00189 }
00190
00191 if( opClass.IsFloat() && opClass.IsLoad() ) {
00192 latency += m_floatConversionLatency;
00193 }
00194
00195 return latency;
00196 }
00197
00198
00199 OpIterator MemExecUnit::GetProducerStore( OpIterator consumer )
00200 {
00201 MemOrderManager* memOrderManager =
00202 consumer->GetThread()->GetMemOrderManager();
00203
00204 return
00205 memOrderManager->GetProducerStore(
00206 consumer,
00207 consumer->GetMemAccess()
00208 );
00209 }