src/Sim/Predictor/HitMissPred/CounterBasedHitMissPred.cpp

説明を見る。
00001 // 
00002 // Copyright (c) 2005-2008 Kenichi Watanabe.
00003 // Copyright (c) 2005-2008 Yasuhiro Watari.
00004 // Copyright (c) 2005-2008 Hironori Ichibayashi.
00005 // Copyright (c) 2008-2009 Kazuo Horio.
00006 // Copyright (c) 2009-2013 Naruki Kurata.
00007 // Copyright (c) 2005-2013 Ryota Shioya.
00008 // Copyright (c) 2005-2013 Masahiro Goshima.
00009 // 
00010 // This software is provided 'as-is', without any express or implied
00011 // warranty. In no event will the authors be held liable for any damages
00012 // arising from the use of this software.
00013 // 
00014 // Permission is granted to anyone to use this software for any purpose,
00015 // including commercial applications, and to alter it and redistribute it
00016 // freely, subject to the following restrictions:
00017 // 
00018 // 1. The origin of this software must not be misrepresented; you must not
00019 // claim that you wrote the original software. If you use this software
00020 // in a product, an acknowledgment in the product documentation would be
00021 // appreciated but is not required.
00022 // 
00023 // 2. Altered source versions must be plainly marked as such, and must not be
00024 // misrepresented as being the original software.
00025 // 
00026 // 3. This notice may not be removed or altered from any source
00027 // distribution.
00028 // 
00029 // 
00030 
00031 
00032 //
00033 // Hit/miss predictor 
00034 //
00035 
00036 #include <pch.h>
00037 #include "Sim/Predictor/HitMissPred/CounterBasedHitMissPred.h"
00038 #include "Sim/ISAInfo.h"
00039 #include "Sim/Op/Op.h"
00040 
00041 using namespace Onikiri;
00042 
00043 CounterBasedHitMissPred::CounterBasedHitMissPred() :
00044     m_counterBits(0), 
00045     m_entryBits(0)
00046 {
00047 }
00048     
00049 CounterBasedHitMissPred::~CounterBasedHitMissPred()
00050 {
00051     ReleaseParam();
00052 }
00053 
00054 void CounterBasedHitMissPred::Initialize(InitPhase phase)
00055 {
00056     if(phase == INIT_PRE_CONNECTION){
00057         LoadParam();
00058 
00059         u8 max = (1 << m_counterBits) - 1;
00060         m_table.construct(
00061             1 << m_entryBits,   // size
00062             (max + 1) / 2,      // init
00063             0,                  // min
00064             max,                // max
00065             1,                  // add
00066             2,                  // sub
00067             (max + 1) / 2       // threshold
00068         );
00069     }
00070 }
00071 
00072 u64 CounterBasedHitMissPred::ConvolutePCToArrayIndex(PC pc)
00073 {
00074     int shift = SimISAInfo::INSTRUCTION_WORD_BYTE_SHIFT;
00075     u64 p = pc.address >> shift;
00076     p ^= pc.tid;
00077     return shttl::xor_convolute(p, m_entryBits);
00078     //return mask(pc.address, m_entryBits);
00079 }
00080 
00081 u64 CounterBasedHitMissPred::MaskPCToArrayIndex(PC pc)
00082 {
00083     int shift = SimISAInfo::INSTRUCTION_WORD_BYTE_SHIFT;
00084     u64 p = pc.address >> shift;
00085     p ^= pc.tid;
00086     return shttl::mask(0, m_entryBits) & p; 
00087 }
00088 
00089 u64 CounterBasedHitMissPred::GetArrayIndex(PC pc)
00090 {
00091     if( m_addrXORConvolute ) {
00092         return ConvolutePCToArrayIndex(pc);
00093     }else {
00094         return MaskPCToArrayIndex(pc); 
00095     }
00096 }
00097 
00098 void CounterBasedHitMissPred::Commit( OpIterator op, bool hit )
00099 {
00100     size_t index = (size_t)GetArrayIndex( op->GetPC() );
00101     if(hit)
00102         m_table[index].inc();
00103     else
00104         m_table[index].dec();
00105 }
00106 
00107 bool CounterBasedHitMissPred::Predict( OpIterator op )
00108 {
00109     size_t index = (size_t)GetArrayIndex( op->GetPC() );
00110     return m_table[index].above_threshold();
00111 }
00112 

Onikiri2に対してTue Jun 18 14:34:25 2013に生成されました。  doxygen 1.4.7