src/Sim/ExecUnit/MemExecUnit.cpp

説明を見る。
00001 // 
00002 // Copyright (c) 2005-2008 Kenichi Watanabe.
00003 // Copyright (c) 2005-2008 Yasuhiro Watari.
00004 // Copyright (c) 2005-2008 Hironori Ichibayashi.
00005 // Copyright (c) 2008-2009 Kazuo Horio.
00006 // Copyright (c) 2009-2013 Naruki Kurata.
00007 // Copyright (c) 2005-2013 Ryota Shioya.
00008 // Copyright (c) 2005-2013 Masahiro Goshima.
00009 // 
00010 // This software is provided 'as-is', without any express or implied
00011 // warranty. In no event will the authors be held liable for any damages
00012 // arising from the use of this software.
00013 // 
00014 // Permission is granted to anyone to use this software for any purpose,
00015 // including commercial applications, and to alter it and redistribute it
00016 // freely, subject to the following restrictions:
00017 // 
00018 // 1. The origin of this software must not be misrepresented; you must not
00019 // claim that you wrote the original software. If you use this software
00020 // in a product, an acknowledgment in the product documentation would be
00021 // appreciated but is not required.
00022 // 
00023 // 2. Altered source versions must be plainly marked as such, and must not be
00024 // misrepresented as being the original software.
00025 // 
00026 // 3. This notice may not be removed or altered from any source
00027 // distribution.
00028 // 
00029 // 
00030 
00031 
00032 #include <pch.h>
00033 
00034 #include "Sim/ExecUnit/MemExecUnit.h"
00035 
00036 #include "Sim/Thread/Thread.h"
00037 #include "Sim/Pipeline/Scheduler/Scheduler.h"
00038 #include "Sim/Memory/Cache/Cache.h"
00039 #include "Sim/Memory/Cache/CacheSystem.h"
00040 #include "Sim/Memory/MemOrderManager/MemOrderManager.h"
00041 #include "Sim/Core/Core.h"
00042 #include "Sim/Op/Op.h"
00043 #include "Sim/Pipeline/Pipeline.h"
00044 #include "Sim/ExecUnit/ExecLatencyInfo.h"
00045 #include "Sim/Foundation/Hook/Hook.h"
00046 #include "Sim/InorderList/InorderList.h"
00047 #include "Sim/Recoverer/Recoverer.h"
00048 
00049 
00050 using namespace std;
00051 using namespace Onikiri;
00052 
00053 MemExecUnit::MemExecUnit() :
00054     m_cacheSystem(0),
00055     m_cache(0),
00056     m_cacheCount(0),
00057     m_floatConversionLatency( 0 )
00058 {
00059 }
00060 
00061 MemExecUnit::~MemExecUnit()
00062 {
00063     ReleaseParam();
00064 }
00065 
00066 void MemExecUnit::Initialize(InitPhase phase)
00067 {
00068     if(phase == INIT_PRE_CONNECTION){
00069     }
00070     else if(phase == INIT_POST_CONNECTION){
00071         CheckNodeInitialized( "memOrderManager", m_memOrderManager );
00072         CheckNodeInitialized( "cacheSystem", m_cacheSystem );
00073 
00074         // LbV
00075         m_cache = m_cacheSystem->GetFirstLevelDataCache();
00076         m_cacheCount = 0;
00077         Cache* cache = m_cache;
00078         for(; cache != 0; cache = cache->GetNextCache(), ++m_cacheCount) {}
00079     }
00080     
00081     PipelinedExecUnit::Initialize(phase);
00082 
00083 }
00084 
00085 
00086 // タsCeV FinishEvent o^
00087 void MemExecUnit::Execute( OpIterator op )
00088 {
00089     ExecUnitBase::Execute( op );    // Not PipelinedExecUnit
00090     RegisterEvents( op, GetExecutedLatency( op ) );
00091 }
00092 
00093 // Get the actual latency of executed 'op'.
00094 int MemExecUnit::GetExecutedLatency( OpIterator op )
00095 {
00096     int latency = 0;
00097 
00098     if(op->GetOpClass().IsLoad()) {
00099         latency = GetExecutedReadLatency(op);
00100     } else if(op->GetOpClass().IsStore()) {
00101         latency = GetExecutedWriteLatency(op);
00102     } else {
00103         THROW_RUNTIME_ERROR("Unknwon opclass.");
00104     }
00105 
00106     return latency;
00107 }
00108 
00109 
00110 // Read タsCeV
00111 // float AISA KCeV
00112 // alpha21264 float  load 1TCN
00113 int MemExecUnit::GetExecutedReadLatency( OpIterator op )
00114 {
00115     int readLatency = 0;
00116 
00117     //  StoreBuffer AhXvs Store 
00118     //  cache ANZX
00119     OpIterator producer = GetProducerStore( op );
00120 
00121     // Only the first access is set to op, because the second or later cache 
00122     // accesses are always partial hit and they are not useful for statistics.
00123     bool firstAccess = 
00124         op->GetCacheAccessResult().state == CacheAccessResult::ST_NOT_ACCESSED;
00125 
00126     if( !producer.IsNull() ) {
00127         readLatency = GetLatency( op->GetOpClass(), 0 );
00128 
00129         if( firstAccess ){
00130             CacheAccessResult result( 0, CacheAccessResult::ST_HIT, NULL );
00131             op->SetCacheAccessResult( result );
00132         }
00133     } 
00134     else {
00135         CacheAccess access( op->GetMemAccess(), op, CacheAccess::OT_READ );
00136         CacheAccessResult result = m_cache->Read( access, NULL );
00137         readLatency = result.latency;
00138         
00139         if( firstAccess ){
00140             op->SetCacheAccessResult( result );
00141         }
00142 
00143         // float  Load CeV
00144         if( op->GetOpClass().IsFloat() ) {
00145             readLatency += m_floatConversionLatency;
00146         }
00147     }
00148 
00149     return readLatency;
00150 }
00151 
00152 // WriteタsCeV
00153 int MemExecUnit::GetExecutedWriteLatency(OpIterator op)
00154 {
00155     // StoreBuffer  Write CeV( ISA K)
00156     int code = op->GetOpClass().GetCode();
00157     int writeLatency = m_execLatencyInfo->GetLatency(code);
00158 
00159     return writeLatency; 
00160 }
00161 
00162 // OpCode CeV
00163 int MemExecUnit::GetLatencyCount(const OpClass& opClass)
00164 {
00165     ASSERT(opClass.IsMem(), "not mem op");
00166     if( opClass.IsStore() ) {
00167         // store CeV
00168         return 1;
00169     }
00170 
00171     // load LbV\
00172     return m_cacheCount;
00173 }
00174 
00175 // OpCode CfNXCeV
00176 int MemExecUnit::GetLatency(const OpClass& opClass, int index)
00177 {
00178     ASSERT( opClass.IsMem(), "not mem op");
00179     if( opClass.IsStore() ) {
00180         // store CeV ExecLatencyInfo 
00181         return m_execLatencyInfo->GetLatency(opClass.GetCode());
00182     }
00183     
00184     int latency = 0;
00185     Cache* cache = m_cache;
00186     for(int i = 0; i <= index; ++i, cache = cache->GetNextCache()) {
00187         ASSERT(cache != 0, "cache not set.(index: %d)", index);
00188         latency += cache->GetStaticLatency();
00189     }
00190     
00191     if( opClass.IsFloat() && opClass.IsLoad() ) {
00192         latency += m_floatConversionLatency;
00193     }
00194 
00195     return latency;
00196 }
00197 
00198 // Get a producer store of 'consumer'.
00199 OpIterator MemExecUnit::GetProducerStore( OpIterator consumer )
00200 {
00201     MemOrderManager* memOrderManager = 
00202         consumer->GetThread()->GetMemOrderManager();
00203 
00204     return
00205         memOrderManager->GetProducerStore(
00206             consumer,
00207             consumer->GetMemAccess()
00208         );
00209 }

Onikiri2に対してTue Jun 18 14:34:22 2013に生成されました。  doxygen 1.4.7