Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga: “Design and Evaluation of a Configurable Query Processing Hardware for Data Streams”, IEICE Trans. on Information and Systems, Vol. E98-D, No. 12, pp. 2207-–2217, Dec., 2015.
Ahmadou Dit Adi Cisse, Michihiro Koibuchi, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga: ” A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation”, IEICE Trans. on Information and Systems, Vol. E96-D, No. 12, pp. 2545–2554, Dec., 2013.
Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsugomu Yoshinaga: “Using Cacheline Reuse Characteristics for Prefetcher Throttling”, IEICE Trans. on Information and Systems, Vol.E95-D, No. 12, pp. 2928–2938, Dec., 2012.
Junichi Ohmura, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga: “Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster”, IEICE Trans. on Information and Systems, Vol. E94-D, No. 12, pp. 2319–2327, Dec., 2011.
Ahmadou Dit Adi Cisse, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, and Tsutomu Yoshinaga: ” An Efficient Path Setup for a Hybrid Photonic Network-on-Chip”, Int. J. of Networking and Computing, Vol. 1, No. 2, pp. 244–259, Jul., 2011.
Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai: “A Sound and Complete Algorithm for Code Generation in Distance-Based ISA”, ACM Int. Conf. on Compiler Construction, pp. 73–84, Feb., 2023.
Junichiro Kadomoto, Hidetsugu Irie, Suichi Sakai: “Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores”, IEEE Int. Symp. on Embedded Multicore/Many-core Systems-on-Chip, pp. 78–84, Dec., 2022.
Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya: “T-SKID: Predicting When to Prefetch Separately from Address Prediction”, Design, Automation and Test in Europe Conference, pp. 1393–1398, Mar., 2022.
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai: “Multiport Register File Design for High-Performance Embedded Cores”, Int. Symp. on Multicore/Many-core Systems-on-Chip, pp. 281–286, Dec., 2021.
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai: “Accurate and Fast Performance Modeling of Processors with Decoupled Front-end”, Int. Conf. on Computer Design, pp. 88–92, Oct., 2021.
Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai: “Compiling and Optimizing Real-world Programs for STRAIGHT ISA”, Int. Conf. on Computer Design, pp. 400–408, Oct., 2021.
Tomoki Nakamura, Kazutaka Tomida, Shota Kohno, Hidetsugu Irie, Shuichi Sakai: “Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation”, Int. Conf. on Computer Design, pp. 74–82, Oct., 2021.
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai: “Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface”, Int. Conf. on Computer Design, pp. 589–596, Oct., 2020.
Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai: “A High-Performance Out-of-Order Soft Processor Without Register Renaming”, Int. Conf. on Field-Programmable Logic and Applications, pp. 73–78, Sep., 2020.
Tomoki Nakamura, Toru Koizumi, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya, “D-JOLT: Distant Jolt Prefetcher”, The 1st Instruction Prefetching Championship (in conjunction with ISCA 2020), pp. 1–5, June, 2020. (3rd place)
Susumu Mashimo, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima, Koji Inoue and Ryota Shioya: “An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor”, Int. Conf. on Field-Programmable Technology, pp. 63–71, Dec., 2019. (Best paper candidates)
Junichiro Kadomoto, Hidetsugu Irie and Shuichi Sakai: “WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers”, Int. Conf. on Computer Design, pp. 102–110, Nov., 2019.
Tomoki Nakamura,Toru Koizumi, Yuya Degawa, Hidetsugu Irie, Suichi Sakai and Ryota Shioya: “T-SKID: Timing Skid Prefetcher”, The Third Data Prefetching Championship (in conjunction with ISCA 2019), June, 2019.
Toru Koizumi, Satoshi Nakae, Akifumi Fukuda, Hidetsugu Irie, Shuichi Sakai: “Reduction of instruction increase overhead by STRAIGHT compier”, Int. Workshop on Computer Systems and Architectures, pp. 92–98, Nov., 2018.
Takahiro Yamada, Hidetsugu Irie, Eiji Nagano, Masahiro Kunitake and Shuichi Sakai: “Estimating Driver’s Readiness by Understanding Driving Posture”, Int. Conf. on Consumer Electronics, pp. 631–634, Jan., 2018.
Kengo Zenitani, Hirokazu Okumura, Hisafumi Mitsushio, Satoru Myojin, Hidetsugu Irie, Shuichi Sakai: “Security Hazard Map by Qualitative Sensitivity Analysis”, Int. Conf. on Project Management, pp. 970–977, Nov., 2016.
Takahiro Yamada, Hidetsugu Irie, Shuichi Sakai: “High-Accuracy Joint Position Estimation and Posture Detection System for Driving”, Int. Workshop on Mobile Ubiquitous Systems, Infrastructures, Communications, and AppLications, pp. 214–219, Nov., 2016.
Mizuki Miyanaga, Hidestugu Irie, Shuichi Sakai, “Accelerating Integrity Verification on Secure Processors by Promissory Hash”, IEEE Pacific Rim Int. Symp. on Dependable Computing, pp. 20–29, Jan., 2017.
Hayato Nomura, Hiroyuki Katchi, Hidetsugu Irie, Shuichi Sakai: “Stubborn Strategy to Mitigate Remaining Cache Misses”, Int. Conf. on Computer Design, pp. 388–391, Oct., 2016.
Masato Yoshimi, Ryu Kudo, Yasin Oge, Yuta Terada, Hidetsugu Irie, Tsutomu Yoshinaga: Accelerating OLAP workload on interconnected FPGAs with Flash storage, Int. Workshop on Computer Systems and Architectures, pp. 1–7, Dec., 2014.
Masato Yoshimi, Ryu Kudo, Yasin Oge, Yuta Terada, Hidetsugu Irie, Tsutomu Yoshinaga: “An FPGA-based Tightly Coupled Accelerator for Data-Intensive Applications”, Int. Symp. on Embedded Multicore/Many-core Systems-on-Chip, pp. 289–296, Sep., 2014.
Takuma Nakajima, Masato Yoshimi, Hidetsugu Irie, and Tsutomu Yoshinaga: “Sharing Computing Resources with Virtual Machines by Transparent Data Access”, Int. Symp. on Computing and Networking, pp. 359–365, Dec., 2013.
Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga: “An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA”, Int. Symp. on Computing and Networking, pp. 112–121, Dec., 2013.
Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga: “Wire-Speed Implementation of Sliding-Window Aggregate Operator over Out-of-Order Data Streams”, Int. Symp. on Embedded Multicore/Many-core SoCs, pp. 55-60, Sep., 2013
Akira Egashira, Shunji Satoh, Hidetsugu Irie and Tsutomu Yoshinaga: “Parallel Numerical Simulation of Visual Neurons for Analysis of Optical Illusion”, Int. Conf. on Networking and Computing, pp. 130–136, Dec., 2012.
Hidetsugu Irie, Daisuke Fujiwara, Kazuki Majima, and Tsutomu Yoshinaga: “STRAIGHT: Realizing a Lightweight Large Instruction Window by using Eventually Consistent Distributed Registers”, Int. Workshop on Challenges on Massively Parallel Processors, pp. 336–342, Dec., 2012.
Yicheng Guan, Cisse Ahmadou Dit Adi, Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie and Tsutomu Yoshinaga, “Throttling Control for Bufferless Routing in On-Chip Networks”, Int. Symp. on Embedded Multicore SoCs, pp. 37–44, Sep., 2012.
Takefumi Miyoshi, Keigo Shima, Masaaki Kondo, Hidetsugu Irie, Hiroki Honda, and Tsutomu Yoshinaga: “FLAT: a GPU programming framework to provide embedded MPI”, Annual Workshop on General Purpose Processing with Graphics Processing Units, pp. 20–29, Mar., 2012.
Junichi Ohmura, Akira Egashira, Shunji Satoh, Takefumi Miyoshi, Hidetsugu Irie, and Tsutomu Yoshinaga, “Multi-GPU Acceleration of Optical Flow Computation in Visual Functional Simulation”, Workshop on Ultra Performance and Dependable Acceleration Systems, pp. 228–234, Dec., 2011.
Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga: “CCCPO: Roubust Prefetcher Optimization Technique Based on Cache Convection”, Int. Conf. on Networking and Computing, pp. 127–133, Nov., 2011.
Takefum Miyoshi, Kenji Kise, Hidetsugu Irie, and Tsutomu Yoshinaga “CODIE: Continuation-based Overlapping Data-transfers with Instruction Execution”, International Conference on Networking and Computing, pp. 71–77, Nov., 2010.
Cisse Ahmadou Dit Adi,Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi and Tsutomu Yoshinaga, “An Efficient Path Setup for a Hybrid Photonic Network-on-Chip” Proc. of the 2nd Workshop on Ultra Performance and Dependable Acceleration Systems (UPDAS’10), pp. 156–161, Nov., 2010.
Qin Wang, Junichi Ohmura, Shan Axida, Takefumi Miyoshi, Hidetsugu Irie, and Tsutomu Yoshinaga, “Parallel Matrix-Matrix Multiplication Based on HPL with a GPU-Accelerated PC Cluster”, Int. Workshop on Parallel and Distributed Algorithms and Applications, pp. 243–248, Nov., 2010.
Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, and Shinji Tomita: “Low-Complexity Bypass Network Using Small RAM”, Int. Conf. on Computer Design (CDES’08), pp. 153–159, Jul., 2008.
Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai: “Preventing Timing Errors on Register Writes: Mechanisms of Detections and Recoveries”, Int. Workshop on Advanced Low Power Systems(ALPS2007), pp. 31–38, June, 2007.
Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai: “Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches”, Proc. of Design, Automation and Test in Europe 2007(DATE 2007), pp. 1134–1149, Apr., 2007.
Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai: “Base Address Recognition with Data Flow Tracking for Injection Attack Detection”, IEEE Int. Symp. on Pacific Rim Dependable Computing, pp. 165–172, Dec., 2006.
杉田 脩, 小泉 透, 入江 英嗣, 坂井 修一: 「距離制限を保証するSTRAIGHTコード生成アルゴリズムの提案」, cross-disciplinay Workshop on Computing Systems, Infrastructures, and Programming, Jul., 2020. (Best Research Award)
中村 朋生,塩谷 亮太,入江 英嗣,坂井 修一: 「キャッシュ圧縮による余剰領域を利用した仮想プリフェッチ・バッファ」, cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming, May, 2019. (xSIG 2019 ポスター賞)
出川 祐也,中村 朋生,渋江 陽人,入江 英嗣,坂井 修一: 「フェーズ検出と事前学習を利用したプリフェッチャ動的切り替え手法の検討」, cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming, May, 2019.
小泉 透,塩谷 亮太,入江 英嗣,坂井 修一: 「リネームレスアーキテクチャに適するオペランド表現」, cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming, May, 2019. (Best M1 Student Award)
Junichiro Kadomoto, Ryozi Asano, Hidetsugu Irie, Shuichi Sakai: “Horizontal Inter-Chip Wireless Bus Interface for Free-Form Chiplet-Based Systems”, cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming, May, 2019. (IEEE Computer Society Japan Chapter xSIG Young Researcher Award)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai: “A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers”, IEEE Symp. on Low-Power and High-Speed Chips (COOL CHIPS), pp. 442–444, Apr., 2020.
Junichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai: “An Inductively Coupled Wireless Bus for Chiplet-Based Systems”, Asia and South Pacific Design Automation Conference (University Design Contest), Jan., 2020.
Naoko Kanda, Daiki Sakuma, Masato Yoshimi, Tsutomu Yoshinaga, Hidetsugu Irie: “Variable Color Environment System using Heart Rate Variability”, Int. Conf. on Bioinformatics and Computational Biology, pp. 24–30, Jul., 2013.
Ping Qiu, Cisse Ahmadou Dit Adi, Hidetsugu Irie, and Tsutomu Yoshinaga, “A Token-based Fully Photonic Network-on-Chip with Dynamic Wavelength Allocation”, International Workshop on Modern Science and Technology (IWMST 2012), pp. 39–44, Aug., 2012.
Hidetsugu Irie, Naoya Hattori, Masanori Takada, Naoya Hatta, Takeshi Toyoshima, Shuichi Sakai: “Distributed Speculative Memory Forwarding”, IEEE Symp. on Low-Power and High-Speed Chips(COOL Chips VIII), pp. 473–482, Apr., 2005.
Hidetsugu Irie, Naoya Hattori, Masanori Takada, Naoya Hatta, Takeshi Toyoshima, Shota Watanabe, Shuichi Sakai: “Steering and Forwarding Techniques for Reducing Memory Communication on Clustered Microarchitecture”, 8th Int. Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems(IWIA2005), pp. 17–17, Jan., 2005.
Yuta Shimomichi, Hidetsugu Irie, Shuichi Sakai: “FaMuRa: Music Generation System using Unconstrained Body Motion”, Int. Conf. on New Interfaces for Musical Expression, Work-In-Progress Showcase, June, 2021.
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai: “A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces”, Asian CHI Symposium, Apr., 2020.
Junichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai: “An Inductively Coupled Wireless Bus for Inter-Chiplet Communication”, Int. Conf. on Solid State Devices and Materials (Poster Session), Sep., 2019.
Hayato Nomura, Tomoki Nakamura, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai: “Preliminary Discussion of a Time Stride Prefetching”, IEEE Symp. on Low-Power and High-Speed Chips and Systems, Poster, Apr., 2019.
Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai: “An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming”, Ph.D Forum, Int. Conf. on Field Programmable Technology, pp. 377–380, Dec., 2018.
Midoriko Chikara, Hidetsugu Irie, Makoto Sahoda, Masato Yoshimi and Tsutomu Yoshinaga: “Pre-Promotion: Synergizing Prefetching and Anti-thrashing Replacement Policy”, Int. Conf. on Computer Design WIP session, Oct., 2015.
Hayato Nomura, Takuma Nakajima, Masato Yoshimi, Tsutomu Yoshinaga, Hidetsugu Irie: “Stubborn Cache: A Novel Strategy for Repeating Thrashing Access Patterns”, COOL Chips XVIII poster, pp. 19, Apr., 2015. (Featured Poster Award)
Hirotaka Kashihara, Hiroki Shimizu, Hiroyoshi Houchi, Masato Yoshimi, Tsutomu Yoshinaga and Hidetsugu Irie: “A Real Time Gait Improvement Tool Using a Smartphone”, Augmented Human International Conference Poster Session, pp. 243, Mar., 2013.
Hidetsugu Irie: “Towards Ultra Flexible Computers:a Novel CPU Architecture and an Interconnect Technology”, Int. Conf. for Top and Emerging Computer Scientists (keynote), Dec., 2019.