Publications Academic Year 2007 (Sakai & Goshima Lab.)

Journals

  1. Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima and Shinji Tomita:
    Low-complexity Operand Bypass Using Small RAM,
    IPSJ Transactions on Advanced Computing Systems (ACS 19), Vol. 48, No. SIG13, pp. 58—69 (2007).
  2. Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Suichi Sakai:
    Preventing Timing Errors on Register Writes: Mechanisms of Detections and Recoveries,
    ACM SIGARCH Computer Architecture News(ACM CAN),Vol. 35, No. SIG5, pp. 25—31 (2007).
    [ pdf ]

International Conferences, Workshops

  1. Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches,
    Automation and Test in Europe (DATE), pp. 1134—1149 (2007).
    [ pdf ]
  2. Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima and Shuichi Sakai:
    Preventing Timing Errors on Register Writes:Mechanisms of Detections and Recoveries
    2nd Int’l Workshop on Advanced Low Power Systems (ALPS), pp. 31—38 (2007).
    [ pdf ]
  3. Kenichiro Hirose, Yoshio Mita, and Shuichi Sakai:
    Polarization-Transmissive Thin-Film Sollar Cell with Photodiode Nanowires,
    IEEE / LEOS Int’l Conf. of Optical MEMS and Nanophotonics, pp. 29—30 (2007).
    [ pdf ]
  4. Kenichiro Hirose, Yasuo Manzawa, Masahiro Goshima, and Shuichi Sakai:
    Delay-Compensation Flip-Flops for Timing-Error Tolerant Circuit Design,
    Int’l Conf. on Solid State Devices and Materials (SSDM), pp. 480—481 (2007).
    [ pdf ]

Domestic Conferences

  1. Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima and Shuichi Sakai:
    A Technique for Detecting and Recoverying of Timing Errors on Register Writing,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS), pp. 235—244 (2007).
    [ pdf ]
  2. Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima and Shinji Tomita:
    Low-Complexity Operand Bypass Using Small RAM,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS), pp. 265—274 (2007).
  3. Kazuo Horio, Haruka Hirai, Masahiro Goshima and Shuichi Sakai:
    Twintail Architecture,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS), pp. 303—311 (2007).
    [ pdf ]
  4. Shinichi Wakiya, Masahiro Goshima and Shuichi Sakai:
    Hot-Path Detector Utilizing Branch Predictor,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS), pp. 321—328 (2007).
    [ pdf ]
  5. Kenichi Watanabe, Hironori Ichibayashi, Masahiro Goshima and Shuichi Sakai:
    Design of Processor Simulator “Onikiri”,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS), pp. 194—195 (2007). (Poster).
    [ pdf ]
  6. Ken Sugimoto, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    Implementation of an out-of-order superscalar processor on FPGAs,
    SSymp. on Advanced Computing Systems and Infrastructures (SACSIS), pp. 196—197 (2007). (Poster).
    [ pdf ]

Workshops

  1. Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima and Shuichi Sakai:
    Evaluation of “Write Assurance Buffer” for Dynamic Timing-error Detection,
    IEICE Technical Report ICD2007–29, pp. 77—78 (2007).
    [ pdf ]
  2. Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    Anti-Dualflow Architecture,
    IPSJ SIG Technical Reports 2007–ARC–174, pp. 1—6 (2007).
    [ pdf ]
  3. Yasuhiro Watari, Kazuo Horio, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    Improvement of Twintail Architecture,
    IPSJ SIG Technical Reports 2007–ARC–174, pp. 7—12 (2007).
    [ pdf ]
  4. Daewung Kim, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    A Proposal of Efficient Tag Management Unit for Tagged Architecture,
    IEICE Technical Reports CPSY2007–10, pp. 25—30 (2007).
    [ pdf ]
  5. Sho Tarui, Satoshi Katsunuma, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    Static Range Analysis for Vulnerability Detection,
    IEICE Technical Reports CPSY2007–22, pp. 95—100 (2007).
    [ pdf ]
  6. Pierre Devautour, Shuichi Sakai, and Masahiro Goshima:
    Fault-tolerant FPGA Architecture with Distributed Internal Configuration-Memory Access,
    IPSJ SIG Technical Reports 2008–ARC–177, pp. 1—6 (2008).
  7. Satoshi Katsunuma, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    String-Aware Information Flow Tracking to Detect Injection Attacks,
    IEICE Technical Report CPSY2007–84, pp. 25—30 (2008).

Book

  1. Masahiro Goshima:
    Dijital Circuits,
    SUURIKOUGAKUSHA-SHA, (2008).

Others

  1. Shuichi Sakai:
    Toward the Society with Dependable Information Processing,
    IPSJ Magazine [Joho Shori], Vol. 48, No. 7, pp. 783—785 (2007).
  2. Shuichi Sakai:
    Dependable Computing,
    UT Forum, (2007).