Publications Academic Year 2008 (Sakai & Goshima Lab.)

JournalsInt’l ConfDomestic SympOral PresentationsInvited Talks

Journals

  1. Satoshi Katsunuma, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    SWIFT: String-Wise Information Flow Tracking,
    IPSJ Trans. on Advanced Computing Systems , Vol. 1, No. 2, pp. 261—274 (2008). (in Japanese).
  2. Hironori Ichibayashi, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    Anti-Dualflow Architecture,
    IPSJ Trans. on Advanced Computing Systems Vol. 1, No. 2, pp. 22—33 (2008). (in Japanese).
  3. Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima and Shuichi Sakai:
    Microarchitectural Register Writing Assurance for Typical-case-designing,
    J. IPSJ, Vol. 49, No. 6, pp. 2016—2028 (2008). (in Japanese).
  4. Shichi Sakai, Masahiro Goshima, Hidetsugu Irie:
    Ultra Dependable Processor,
    IEICE Trans. on Electronics, Vol. E91-C, No. 9, pp. 1386—1393 (2008).
  5. Kenichiro Hirose, Yasuo Manzawa, Masahiro Goshima, Shuichi Sakai:
    Delay-Compensation Flip-Flop with In-situ Error Monitoring for Low-Power and Timing-Error-Tolerant Circuit Design,
    IPAP (Institute of Pure and Applied Physics) Japanese Journal of Applied Physics, Vol. 47, No. 4, pp. 2779—2887 (2008).

International Conferences & Symposiums

  1. Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, and Shinji Tomita:
    Low-Complexity Bypass Network Using Small RAM,
    Int’l Conf. on Computer Design (CDES’08),pp. 153—159 (2008).
  2. Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe:
    Dependable VLSI: Device, Design and Architecture — How should they cooperate —,
    Proc. ASP-DAC 2009, pp. 859—860 (2009).

Domestic Symposiums (with peer review)

  1. Satoshi Katsunuma, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    SWIFT: String-Wise Information Flow Tracking,
    Symp. on Advanced Computing Systems & Infrastructures (SACSIS), pp. 167—176 (2008). (in Japanese).
  2. Daewung Kim, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    Low-overhead tagged architecture for variable-length tag,
    Symp. on Advanced Computing Systems & Infrastructures (SACSIS), pp. 177—185 (2008). (in Japanese).
  3. Ryota Shioya, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    Area-Oriented Register Cache,
    Symp. on Advanced Computing Systems & Infrastructures (SACSIS), pp. 229—236 (2008). (in Japanese).
  4. Hironori Ichibayashi, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    Anti-Dualflow Architecture,
    Symp. on Advanced Computing Systems & Infrastructures (SACSIS), pp. 245—254 (2008). (in Japanese).
  5. Kentarou Hara, Ryota Shioya and Kenjirou Taura:
    Comparing Performance of General Purpose Processors with Memory Access Optimizations and the Cell —A Case Study with Cell Speed Challenge—,
    Symp. on Advanced Computing Systems & Infrastructures (SACSIS), pp. 157—166 (2008). (in Japanese).

Oral Presentations

  1. Hidetsugu Irie, Ken Sugimoto, Ryota Shioya, Kenichi Watanabe, Masahiro Goshima and Shuichi Sakai:
    A Lightweight Write Error Detection for Register-file Using Improved Passive WAB,
    IEICE Technical Reports CPSY 2008-3;ARC–178, pp. 13—18 (2008). (in Japanese).
    [ PDF ]
  2. Takanobu Kita, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    Speculation scheme that continues executing mispredicted instructions,
    IPSJ SIG Technical Reports 2008–ARC–178, pp. 7—12 (2008). (in Japanese).
    [ PDF ]
  3. Ryota Shioya, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    Evaluation of Area-Oriented Register Cache,
    IPSJ SIG Technical Reports 2008–ARC–178, pp. 13—18 (2008). (in Japanese).
    [ PDF ]
  4. Li Kunbo, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
    String-Wise Information Flow Tracking,
    STARC Forum/Symposium 2008 (2008). (Poster).
  5. Shuhei Eguchi and Shuichi Sakai:
    Evaluation of AES circuit of Tamper-Resistant Processor,
    STARC Forum/Symposium 2008 (2008). (Poster).
  6. Ken Sugimoto, Hidetsugu Irie, Masahiro Goshima and Shuichi Sakai:
    Timing-Fault-Tolerant Superscalar Processor,
    IEICE Technical Report CPSY2008-14, pp. 19—24 (2008).
  7. Sho Tarui, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
    A Timing-Fault-Tolerant Clocking Scheme,
    IEICE Technical Report CPSY2008-14, pp. 25—30 (2008).
  8. Kazuo Horio, Yasuhiro Watari, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
    Evaluation of Twintail Architecture,
    IPSJ SIG Technical Reports 2008–ARC–179, pp. 7—12 (2008).
  9. Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
    Branch Pre-Decision,
    IPSJ SIG Technical Reports 2008–ARC–179, pp. 67—72 (2008).
  10. Toru Ando, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
    Dynamic Helper Threading Based on Loop Structure,
    IPSJ SIG Technical Reports 2008–ARC–179, pp. 139—144 (2008).
  11. Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai, Kei Hiraki:
    Vulnerability Evaluation of Timing-errors on Register Write,
    IPSJ SIG Technical Reports 2008–ARC–179, pp. 175—180 (2008).
  12. Shuhei Eguch, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
    The effect of main memory bandwidth on processor performance,
    IPSJ SIG Technical Reports 2008–ARC–180 pp. 15—20 (2008).

Invited Talks

  1. Shuichi Sakai, Masahiro Fujita, Masahiro Gosima, Kenji Kise:
    Challenges for an Ultra Dependable VLSI,
    IEICE General Conf., AI-1-4 (2009).
    [ PDF ]