Publications Academic Year 2009 (Sakai & Goshima Lab.)

International Conferences & Symposiums

• IEEE Int’l Symp. on Pacific Rim Dependable Computing (PRDC 2009) in Shanghai
  1. Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai:
     Low-overhead architecture for security tag,
     IEEE Int’l Symp. on Pacific Rim Dependable Computing (PRDC 2009),
     DOI: 10.1109/PRDC.2009.30 (2009).
  2. Kunbo Li, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     String-wise information flow tracking against script injection attacks,
     IEEE Int’l Symp. on Pacific Rim Dependable Computing (PRDC 2009),
     DOI: 10.1109/PRDC.2009.35 (2009).

Domestic Symposiums (with peer review)

• Symposium on Advanced Computing Systems & Infrastructres (SACSIS) 2009
  1. Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     Design and Implementation of a Processor Simulator “Onikiri2”,
     Symp. on Advanced Computing Systems & Infrastructures (SACSIS), pp. 120—121 (2009). (Poster).
     [ PDF ]
  2. Shuhei Eguchi,Ryota Shioya,Masahiro Goshima, and Shuichi Sakai:
     The effect of main memory bandwidth on processor performance,
     Symp. on Advanced Computing Systems & Infrastructures (SACSIS), pp. 147—148 (2009). (Poster).
     [ PDF ]

Oral Presentations

• Summer Workshop on Parallel Processing (SWoPP) 2009
  1. Takanobu Kita, Shou Tarui, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     Exploratory evaluation of a clocking scheme with relaxed timing constraints,
     IEICE Technical Reports CPSY 2009-26, pp. 61—66 (2009).(in Japanese).
     [ PDF ]
  2. Yuki Yokota, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     A Platform for Preventing Information Leakage,
     IEICE Technical Reports CPSY 2009-28, pp. 7—12 (2009).(in Japanese).
     [ PDF ]
  3. Youngkwang Moon, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     Platforms Attestation for Preventing Information Leakage,
     IEICE Technical Reports CPSY 2009-29, pp. 13—18 (2009).(in Japanese).
     [ PDF ]
  4. Yuji Ito, Ryota Shioya, Masahiro Goshima,and Shuichi Sakai:
     Nested Transactional Memory Selecting the Optimal Rollback Point,
     IPSJ SIG Technical Report 2009–ARC–184, (2009). (in Japanese).
     [ PDF ]
  5. Kazuo Horio, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     Design of Area-efficient Processor,
     IPSJ SIG Technical Report 2009–ARC–184, (2009). (in Japanese).
     [ PDF ]
  6. Takashi Okada, Takanobu Kita, Masahiro Goshima, and Shuichi Sakai:
     Fault-tolerant FPGA Architecture,
     IPSJ SIG Technical Report 2009–ARC–184, (2009). (in Japanese).
     [ PDF ]
• CREST 1st DVLSI Test Structure Forum
  1. Takanobu Kita:
     A clocking scheme with relaxed timing constraints,
     CREST 1st DVLSI Test Structure Forum, FD1-4 (2009). (in Japanese).
     [ PDF ]
• The 72nd National Convention of IPSJ
  1. Takanobu Kita, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     A proposal of a clocking scheme with relaxed timing constraints,
     The 72th National Convention of IPSJ, pp. 1-239—1-240 (2010). (in Japanese).
     [ PDF ]
  2. Shuhei Eguchi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     The effect of main memory bandwidth on processor performance,
     The 72th National Convention of IPSJ, pp. 1-179—1-180 (2010). (in Japanese).
     [ PDF ]
  3. Kazuo Horio, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     Design and implementation of Area-efficient superscalar processor,
     The 72th National Convention of IPSJ, pp. 1-181—1-182 (2010). (in Japanese).
     [ PDF ]
  4. Yuki Yokota, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     A Platform for Preventing Information Leakage,
     The 72th National Convention of IPSJ, pp. 3-629—3-630 (2010). (in Japanese).
     [ PDF ]
  5. Yen-chun Wang, Kazuo Horio,Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     Reevaluating the Renamed Trace Cache Architecture,
     The 72th National Convention of IPSJ, pp. 1-191—1-192 (2010).
     [ PDF ]
  6. Youngkwang Moon, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     Platforms Attestation for Preventing Information Leakage,
     The 72th National Convention of IPSJ, pp. 3-632—3-633 (2010). (in Japanese).
     [ PDF ]
  7. Yuji Ito, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     Evaluation of Nested Transactional Memory Selecting the Optimal Rollback Point,
     The 72th National Convention of IPSJ, pp. 1-187—1-188 (2010). (in Japanese).
     [ PDF ]
  8. Takashi Okada, Takanobu Kita, Masahiro Goshima, and Shuichi Sakai:
     Preliminary Evaluation of Fault-tolerant FPGA Architecture,
     The 72th National Convention of IPSJ, pp. 1-221—1-222 (2010). (in Japanese).
     [ PDF ]
  9. ‘q“c ¬ŒÈ, ‰–’J —º‘¾, ŒÜ“‡ ³—T, âˆä Cˆê:
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     The 72th National Convention of IPSJ, pp. 1-213—1-214 (2010). (in Japanese)
     [ PDF ]
  10. —L”n Œd, ‰ª“c ’Žu, –x”ö ˆê¶, Šì‘½ ‹MM, ‰–’J —º‘¾, ŒÜ“‡ ³—T, âˆä Cˆê:
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      The 72th National Convention of IPSJ, pp. 1-223—1-224 (2010). (in Japanese)
      [ PDF ]
  11. Hiroshi Toi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
      Implementation of String-Wise Information Flow Tracking to PHP,
      The 72th National Convention of IPSJ, pp. 3-623—3-624 (2010). (in Japanese).
      [ PDF ]

Award

1. Takanobu Kita:
   Speculation Scheme That Continues Executing Mispredicted Instructions (2008-ARC-178),
   IPSJ Yamashita SIG Research Award 2009 (2009).
2. Shichi Sakai:
   IPSJ Fellow (2009).

Thesis

• Mater Thesis
  1. Takanobu Kita:
     A Clocking Scheme with Relaxed Timing Constraints,
     Master Thesis, Dept. of Information and Communication Eng, The University of Tokyo (2010).
  2. Shuhei Eguchi:
     The Effect of Main Memory Bandwidth on Processor Performance,
     Master Thesis, Dept. of Information and Communication Eng, The University of Tokyo (2010).
  3. Kazuo Horio:
     Design of Area-Efficient Superscalar Processor,
     Master Thesis, Dept. of Information and Communication Eng, The University of Tokyo (2010).
  4. Yuki Yokota:
     A Platform for Preventing Information Leakage,
     Master Thesis, Dept. of Information and Communication Eng, The University of Tokyo (2010).
  5. Yen-chun Wang:
     Evaluating the Renamed Trace Cache Architecture,
     Master Thesis, Dept. of Information and Communication Eng, The University of Tokyo (2010).
  6. Youngkwang Moon:
     Platforms Attestation for Preventing Information Leakage,
     Master Thesis, Dept. of Information and Communication Eng, The University of Tokyo (2010).
• Undergraduate Thesis
  1. Kurata:
     ,
     Undergraduate Thesis, Dept. of Information and Communication Eng, The University of Tokyo (2010).
  2. Satoshi Arima:
     Improvement of Transient-Fault-Tolerant Scheme for Out-of-Order Superscalar Processors,
     Undergraduate Thesis, Dept. of Information and Communication Eng, The University of Tokyo (2010).
  3. Hiroshi Toi:
     Implementation of String-Wise Information Flow Tracking to PHP,
     Undergraduate Thesis, Dept. of Information and Communication Eng, The University of Tokyo (2010).