Publications Academic Year 2010 (Sakai & Goshima Lab.)

Journals

• IEICE Trans. on Information and Systems
  1. Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai:
     Low-overhead architecture for security tag,
     IEICE Trans. on Information and Systems, Vol. E94–D, No. 1, pp. 69—78 (2011).
     DOI: 10.1587/transinf.E94.D.69

International Conferences

• MICRO-43
  1. Ryota Shioya, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai:
     Register Cache System not for Latency Reduction Purpose,
     IEEE Int’l Symp. on Microarchitecture (MICRO-43), pp. 301—312 (2010).
     DOI: 10.1109/MICRO.2010.43
     [ PDF ]

• PRDC 2010 in Tokyo
  1. Hiroshi Toi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     Yet Another Taint Mode for PHP,
     IEEE Int’l Symp. on Pacific Rim Dependable Computing (PRDC) (2010).   (poster).

Domestic Symposiums (with peer review)

• Symp. on Advanced Computing Systems & Infrastructures (SACSIS 2010) at Nara, Japan
  1. Ryota Shioya, Naruki Kurata, Jun Nakashima, Masahiro Goshima, and Shuichi Sakai:
     Switch-on-Future-Event Multithreading,
     Symp. on Advanced Computing Systems & Infrastructures (SACSIS), pp. 157—165 (2010).   (in Japanese).
     [ PDF ]
  2. Kazuo Horio, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     Design of Area-Efficient Processor,
     Symp. on Advanced Computing Systems & Infrastructures (SACSIS), pp. 339—346 (2010).   (in Japanese).
     [ PDF ]
  3. Takanobu Kita, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
     A Clocking Scheme with Relaxed Timing Constrainsts,
     Symp. on Advanced Computing Systems & Infrastructures (SACSIS), pp. 347—354 (2010).   (in Japanese).
     [ PDF ]

Oral Presentations

• IEICE CPSY — SIG: Coumputer System
  1. Takashi Okada, Takanobu Kita, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
     Fault-tolerant FPGA Architecture,
     IEICE Technical Reports CPSY 2010-7, pp. 33—37 (2010).   (in Japanese).
     [ PDF ]
  2. Satoshi Arima, Takashi Okada, Takanobu Kita, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
     Improvement of Transient-Fault-Tolerant Scheme for Out-of-Order Superscalar Processors,
     IEICE Technical Reports CPSY 2010-5, pp. 21—26 (2010).   (in Japanese).
     [ PDF ]
• Summer Workshop on Parallel Processing (SWoPP) 2010
  1. Yuji Ito, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
     Transactional Memory Selecting the Optimal Rollback Point,
     IPSJ SIG Technical Report 2010–ARC–190, No. 9 (2010).   (in Japanese).
     [ PDF ]
  2. Satoshi Arima, Takashi Okada, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
     Commit Scheme for Transient-Fault-Tolerant Out-of-Order Superscalar Processors,
     IPSJ SIG Technical Report 2010–ARC–190, No. 10 (2010).   (in Japanese).
     [ PDF ]
  3. Naruki Kurata, Ryota Shioya, Jun Nakashima, Masahiro Goshima and Shuichi Sakai:
     An Improvement of Switch-on-Future-Event Multithreading,
     IPSJ SIG Technical Report 2010–ARC–190, No. 27 (2010).   (in Japanese).
     [ PDF ]
  4. Hiroshi Toi, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
     Implementation and Evaluation of String-Wise Information Flow Tracking to PHP,
     IPSJ SIG Technical Report 2010–OS–115, No. 4 (2010).   (in Japanese).
     [ PDF ]
• IPSJ The 73rd National Convention
  1. Mitsuo Date, Naruki Kurata, Yuji Ito, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
     Dispatched Image Cache,
     The 73rd National Convention of IPSJ, pp. 1-91—1-92 (2011). (in Japanese).
     [ PDF ]
  2. Takashi Okada, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
     Evaluation of Fault-tolerant FPGA Architecture,
     The 73rd National Convention of IPSJ, pp. 1-51—1-52 (2011). (in Japanese).
  3. Yuji Ito, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
     Transactional Memory Selecting the Optimal Checkpoint,
     The 73rd National Convention of IPSJ, pp. 1-69—1-70 (2011). (in Japanese).
     [ PDF ]
  4. Kaoru Hayakawa, Hiroshi Toi, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
     Partial Platform Attestation,
     The 73rd National Convention of IPSJ, pp. 3-559—3-560 (2011). (in Japanese).
     [ PDF ]
  5. Shuji Yoshida, Satoshi Arima, Takashi Okada, Ryota Shioya, Masahiro Goshima and Shuichi Sakai:
     A Clocking Scheme Enabling Dynamic Time Borrowing,
     The 73rd National Convention of IPSJ, pp. 1-91—1-92 (2011). (in Japanese).
     [ PDF ]

Invited Talk, Panel Discussion

• VDEC D2T Symposium
  1. Shuichi Sakai:
     Ultra Dependable VLSI Processor Architecture,
     VDEC D2T Symposium 2010, invited talk (2010).
  2. Shuichi Sakai, et al.:
     Dependable VLSI Systems,
     VDEC D2T Symposium 2010, panel discussion (2010).
• Information Processing Society Japan SIG Computer Architecture, 183rd meeting
  1. Masahiro Goshima, et al.:
     What can we do in reviewing papers to make ARC more energetic?,
     Information Processing Society Japan, SIG Computer Architecture, 183rd meeting, panel discussion (2010).

Award

• 72nd National Convention of IPSJ, Certificate of Excellent Undergraduate/Master Thesis
  1. Naruki Kurata:
     A multi-threaded processor targeted for loops,
     72nd National Convention of IPSJ, Certificate of Excellent Undergraduate Thesis (2010).
  2. Satoshi Arima:
     Improvement of Transient-Fault-Tolerant Scheme for Out-of-Order Superscalar Processors,
     72nd National Convention of IPSJ, Certificate of Excellent Undergraduate Thesis (2010).
  3. Hiroshi Toi:
     Implementation of String-Wise Information Flow Tracking to PHP,
     72nd National Convention of IPSJ, Certificate of Excellent Undergraduate Thesis (2010).
  4. Takanobu Kita:
     Clocking Scheme with Relaxed Timing Constraints,
     72nd National Convention of IPSJ, Certificate of Excellent Master Thesis (2010).

Thesis

• Doctor Thesis
  1. Ryota Shioya:
     A Research of Area-Efficient Processor,
     Doctor thesis, Dept. of Information and Communication Eng, the University of Tokyo, (2011).
     [ PDF ]
• Mater Thesis
  1. Ito Yuji:
     Research on Transactional Memory Relaxing Restriction of Programming,
     Master thesis, Dept. of Information and Communication Eng, the University of Tokyo, (2011).
     [ PDF ]
  2. Okada Takashi:
     Fault-tolerant FPGA Architecture,
     Master thesis, Dept. of Information and Communication Eng, the University of Tokyo, (2011).
     [ PDF ]
  3. Akamatsu Yuichi A phase detection technique not using fixed length intervals,
     Master thesis, Dept. of Information and Communication Eng, the University of Tokyo, (2011).
     [ PDF ]