Adaptive Controls for Large Lower-level Caches

For improving performance of the processors, it is important to reduce cache misses and enclose as much memory requests as possible within the on-chip cache transaction. In recent years, while the capacity of cache memories has increased and on chip memories can hold almost all working sets of some programs, some kinds of cache misses which are difficult to solve still degrade the performance of processors.

For long time, the earliest algorithms based on locality have been mostly used as cache management algorithms, but to exploit large capacity caches so called Last Level Cache(LLC) which occupy a fraction of the chip it is revealed that the algorithm which takes longer interval program’s behavior into consideration is better than old one. So, new algorithms for cache management such as prefetch, replacement and so on appear one after another in 2010s.

But the efficiency of the cache management algorithms differs greatly by the tendency of the programs and by the presence or absence of the optimization technology of the cache. So, it is said that such algorithms decline the performance of the processors in some cases. And the such difference is very large in newer complex algorithms.

In our research, to improve performance of the processors by using LLC efficiently, we study the technique which estimates the tendency of programs while processors perform them and choose the most suitable combination of the managements automatically.

We examined the algorithm that determines cachelines to be protected for our Stubborn strategy. Moreover, as a fundamental technology to make cache managements adaptive, we proposed a novel phase detection algorithm by monitoring memory access behavior.


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