STRAIGHT: Highly Efficient General-purpose Processor Architecture

Improving the performance and power-efficiency of CPUs which are the heart of information processing is the basis of the improvement of computer systems. Recently, approaches which combines power-efficient, simple in-order processors and accelerators which are specified for certain applications to enhance the total performance of the processor package have become to be adopted because the direct benefit from semiconductor scaling had shown the sign of slowing. Although the conventional out-of-order superscalar architecture that enables flexible instruction-level-parallel execution is still most effective for accelerating the sequential part of the program that often becomes a bottleneck as well as user programs to which quick development is necessary, it requires significant fraction of its power in addition to those required in arithmetic (execution) units because of its smartness, which limits its adoption into various systems but servers, desktops, or high-end mobiles. It can raise the level of the flexibility and the efficiency of processors for various fields to realize a novel computer architecture which has simple instruction management while maintaining its flexible instruction-level-parallel executions and speculations

In this research, we propose and developing “STRAIGHT” architecture that has the merit of the high performance and the flexibility of the out-of-order execution while achieving power-efficiency by excluding the management cost in the exchange of increasing the capacity of the register-file. The basic proposal of STRAIGHT is to introduce the restriction to the program code in which the registers cannot be overwritten and the value of them cannot be read after a certain period. Keeping the almost meaning of instructions unchanged, introducing such tiny restriction makes conventional mapped register renaming and the management of register lifetime unnecessary, which greatly reduces power consumption without lowering the performance. Besides, such excluding the management makes extending the instruction-window size and register-file easy, which increases the utilization of the arithmetic units and reduces the memory transfer, thus the architecture can exchange the additional transistor to the performance improvement.

We have confirmed the feasibility of the frontend pipeline structure as well as evaluated the overhead of the implementation of several state registers which can be exceptionally overwritten, by developing the HDL specification of STRAIGHT microarchitecture. Besides, we have developed the compiler that generates the code from SSA-formatted intermediate expression to satisfy the unique restrictions of STRAIGHT,  which is one of the most challenging techniques in this research. In 2017, we presented the fundamental algorithm of STRAIGHT as well as an optimization technique for looped code that reduces memory transactions. Moreover, using the speculative memory forwarding technology, a microarchitectural optimization is developed.



  • Hidetsugu IRIE, Daisuke FUJIWARA, Kazuki MAJIMA, and Tsutomu YOSHINAGA: “STRAIGHT: Realizing a Lightweight Large Instruction Window by using Eventually Consistent Distributed Registers”, Int. Workshop on Challenges on Massively Parallel Processors, pp. 336 — 342, Dec., 2012.