Prefetching Technique Focusing on Timing

To obtain the best performance from the processor, it is important that the data and instructions to be processed reside in the cache memory. However, in exchange for high speed, cache memory has a small capacity and can only retain some portion of the data or instructions. Therefore, a prefetching technique that predicts future data and instructions and moves them to cache memory has been widely studied. However, existing research has been only limited to predicting which data and instructions should be prefetched. Our study aims to achieve even better performance by introducing the concept of prefetch timing. As a special feature of our research, we created a memory access pattern visualization tool called sazanami, which we use in our research (see the figure above).


Search this site

Recent News


  • 記事はありません