Floorplaning of 3D Processor Cores
Advances in semiconductor manufacturing technology made it possible to connect by wiring between stacked semiconductor layers directly. It is expected that 3D-staking of VLSI processors leads increasing package area over limit of scaling cost and reducing power for signal transportation compared with traditional 2D placing and routing.
However, it is not clear what architecture and block design is optimal because of its huge design spaces.
In this study, we proposed a module mapper using SA method (Simulated Annealing Method) to get an estimation of the wiring cost of a floor plan and effect of it.
We have proposed and evaluated a technique that decides TSV (Through Silicon Via) position with less calculation amount.