DTB

As the feature size of LSI becomes smaller, random variation of each element becomes more influential. The variation of elements decreases the yield, and makes conventional design based on worst-case estimation too pessimistic. The mechanism of detecting and recovering timing-faults makes the most of the advantages of becoming smaller feature size of LSI and make high-performance and low power operation possible.

In this study, we have proposed a technique that enables dynamic time borrowing which cuts the overhead of recovering error by tolerating accumulation of timing-delay. Our technology realizes more efficient timing-fault tolerant VLSI than conventional related technologies. We can realize this technology by combining two-phase latch system and dynamic timing-fault detection. We verify the timing-fault tolerant processor which is implemented with introducing this technique into critical path, and make a study of automation technique of the latch insertion to a critical path.

We are now developing a program for applying the proposed method to existing circuits. We try to implement and evaluate the search algorithm for determining the position of the latch insertion.